[ARM] Some bitwise logic instructions used by cmp-ne-zero are not combined into S-suffixed versions

[fzhinkin]

Majority of bitwise logic instructions have 'S'-version which update status flags but only subset of these instructions is supported by the ARMBaseInstrInfo::optimizeCompareInstr peephole.

For example, ORR with shifted second operand is not supported by the peephole:
https://godbolt.org/z/536GvzfP4

bool cmp_ne_orr_rsr(uint32_t a, uint32_t b) {
    return (a | (b << 2)) != 0;
}

is currently compiled into:

cmp_ne_orr_rsr(unsigned int, unsigned int):
        orr     r0, r0, r1, lsl #2
        cmp     r0, #0
        movwne  r0, #1
        bx      lr

but a bit more optimal code will look like:

cmp_ne_orr_rsr(unsigned int, unsigned int):
        orrs    r0, r0, r1, lsl #2
        movwne  r0, #1
        bx      lr

The same is true for AND, ORR, EOR with shifted register operand and all versions of BIC.

The peephole also ignores shift instructions (except T2's LSR and LSL).

[llvmbot]

@llvm/issue-subscribers-backend-arm

[fzhinkin]

Proposed fix: https://reviews.llvm.org/D131786
If there are no objects I'll remove the "draft" status from it.

[davemgreen]

Sounds OK to me. It's probably worth making sure that it is well tested - perhaps by running a bootstrap.

[fzhinkin]

Fixed: 945a146