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Miscompile after changes to MachineCopyPropagation in commit cae46f6210293ba4d3568eb2 #73512
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I reverted the offending commit. |
Sorry for the late reply. I would like to ask if there are a lot of other miscompiles in the downstream? |
I don't have any other reproducers that I can share (and that would be meaningful). Took me quite some time just to reduce the test case for the downstream target. And then I needed to figure out how to convert that into something showing the problem for an in-tree target. With that said, my first suspicion here was around implicit operands. Not quite sure if that is the case here (i.e. those S_NOP:s with implicit operands can probaby be any instruction with non-implicit defs/uses, if you just know how to write AMDPPU mir). Anyway, afaict lots of code in MachineCopyPropagation is inspecting all operands (including implicit operands). But then there are several places where things like |
Yeah, I'll try to debug the pass and figure out the root cause for this test case later. Essentially, when we encounter: Consequently, it prevents the removal of the subsequent instruction during the basic block scanning procedure. Thank you for taking the time to investigate this issue. |
…74239) Machine Copy Propagation Pass may lose some opportunities to further remove the redundant copy instructions during the ForwardCopyPropagateBlock procedure. When we Clobber a "Def" register, we also need to remove the record from the copy maps that indicates "Src" defined "Def" to ensure the correct semantics of the ClobberRegister function. This patch reapplies #70778 and addresses the corner case bug #73512 specific to the AMDGPU backend. Additionally, it refines the criteria for removing empty records from the copy maps, thereby enhancing overall safety. For more information, please see the C++ test case generated code in "vector.body" after the MCP Pass: https://gcc.godbolt.org/z/nK4oMaWv5.
Fixed by #74239. |
We started to see miscompiles downstream after the update to MachineCopyPropagation here: cae46f6
I managed to reduce one failure and convert it into this (just picking AMDGCPU as target to get something with register tuples):
Without the changes to MCP:
After cae46f6:
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