[AArch64][SME] Various tests should work with +sme, just as they do for +sve #65260
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MDevereau
reviewed
Sep 5, 2023
| @@ -6202,7 +6202,7 @@ bool AArch64TargetLowering::useSVEForFixedLengthVectorVT( | |||
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| // All SVE implementations support NEON sized vectors. | |||
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Suggested change
| // All SVE implementations support NEON sized vectors. | |
| // All SVE/SME implementations support NEON sized vectors. |
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I'm not sure we want to go overboard with giving the impression SME is distinct from SVE because the nuances are going to confuse people, with this a prime example. Whilst SVE does truly support NEON size vectors, the same is not true for SME where the support is simulated though the use of predication. In general when we mean "SVE instructions" I'd rather we just say SVE and then better document the SVE instructions that are not provided by SME, which are significant fewer in number.
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I have tried to clarify the comment without making it sound like SME is distinct from SVE.
| @@ -3961,7 +3961,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, | |||
| if (AArch64::FPR16RegClass.hasSubClassEq(RC)) | |||
| Opc = AArch64::STRHui; | |||
| else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { | |||
| assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); | |||
| assert(Subtarget.hasSVEorSME() && "Unexpected register store without SVE"); | |||
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| assert(Subtarget.hasSVEorSME() && "Unexpected register store without SVE"); | |
| assert(Subtarget.hasSVEorSME() && "Unexpected register store without SVE or SME"); |
This should be updated to reflect the actual assertion behaviour.
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I have changed the message to reason about "SVE store instructions" (rather than "SVE or SME")
|
@llvm/pr-subscribers-backend-aarch64 ChangesNonePatch is 47.55 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/65260.diff 57 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0c8432daeb8c56c..5d0f7d3ba09bc35 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1272,7 +1272,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
}
}
- if (Subtarget->hasSVE()) {
+ if (Subtarget->hasSVEorSME()) {
for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64}) {
setOperationAction(ISD::BITREVERSE, VT, Custom);
setOperationAction(ISD::BSWAP, VT, Custom);
@@ -6200,9 +6200,9 @@ bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(
break;
}
- // All SVE implementations support NEON sized vectors.
+ // NEON-sized vectors can be emulated using SVE instructions.
if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector()))
- return Subtarget->hasSVE();
+ return Subtarget->hasSVEorSME();
// Ensure NEON MVTs only belong to a single register class.
if (VT.getFixedSizeInBits() <= 128)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 72c791af4b43b0e..95fc3ecc2a0dd24 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -3961,7 +3961,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
Opc = AArch64::STRHui;
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register store without SVE store instructions");
Opc = AArch64::STR_PXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4005,7 +4006,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
AArch64::sube64, AArch64::subo64, FI, MMO);
return;
} else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register store without SVE store instructions");
Opc = AArch64::STR_ZXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4028,7 +4030,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Offset = false;
} else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register store without SVE store instructions");
Opc = AArch64::STR_ZZXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4039,7 +4042,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Opc = AArch64::ST1Threev2d;
Offset = false;
} else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register store without SVE store instructions");
Opc = AArch64::STR_ZZZXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4051,7 +4055,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Offset = false;
} else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register store without SVE store instructions");
Opc = AArch64::STR_ZZZZXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4119,7 +4124,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
Opc = AArch64::LDRHui;
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_PXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4163,7 +4169,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
AArch64::subo64, FI, MMO);
return;
} else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_ZXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4186,7 +4193,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Offset = false;
} else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_ZZXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4197,7 +4205,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Opc = AArch64::LD1Threev2d;
Offset = false;
} else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_ZZZXI;
StackID = TargetStackID::ScalableVector;
}
@@ -4209,7 +4218,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Offset = false;
} else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
+ assert(Subtarget.hasSVEorSME() &&
+ "Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_ZZZZXI;
StackID = TargetStackID::ScalableVector;
}
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index dc54da477eaa15d..5d0fd7f9f45b59c 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -402,10 +402,10 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool useSVEForFixedLengthVectors() const {
if (!isNeonAvailable())
- return hasSVE();
+ return hasSVEorSME();
// Prefer NEON unless larger SVE registers are available.
- return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
+ return hasSVEorSME() && getMinSVEVectorSizeInBits() >= 256;
}
bool useSVEForFixedLengthVectors(EVT VT) const {
diff --git a/llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll b/llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
index 768d54d423f2943..6d534060293d61d 100644
--- a/llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
+++ b/llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
define @extract_row_b( %zd, %pg, i32 %tileslice) {
; CHECK-LABEL: extract_row_b:
diff --git a/llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll b/llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
index a88834c9626f86b..15c33e343c48f04 100644
--- a/llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
+++ b/llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
define void @insert_row_b(i32 %tileslice, %pg,
; CHECK-LABEL: insert_row_b:
diff --git a/llvm/test/CodeGen/AArch64/sme-streaming-body.ll b/llvm/test/CodeGen/AArch64/sme-streaming-body.ll
index ff23ed9dfe5a2d5..fa43f7a90c3d7dd 100644
--- a/llvm/test/CodeGen/AArch64/sme-streaming-body.ll
+++ b/llvm/test/CodeGen/AArch64/sme-streaming-body.ll
@@ -87,25 +87,29 @@ if.end:
define <2 x i64> @locally_streaming_caller_no_callee(<2 x i64> %a) "aarch64_pstate_sm_body" nounwind {
; CHECK-LABEL: locally_streaming_caller_no_callee:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp d15, d14, [sp, #16] // 16-byte Folded Spill
-; CHECK-NEXT: stp d13, d12, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
-; CHECK-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
+; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: str x29, [sp, #64] // 8-byte Folded Spill
+; CHECK-NEXT: addsvl sp, sp, #-1
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: smstart sm
-; CHECK-NEXT: adrp x8, .LCPI3_0
-; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT: add v0.2d, v1.2d, v0.2d
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-NEXT: index z0.d, #0, #1
+; CHECK-NEXT: ldr z1, [sp] // 16-byte Folded Reload
+; CHECK-NEXT: add z0.d, z0.d, z1.d
+; CHECK-NEXT: add z0.d, z0.d, #41 // =0x29
+; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: smstop sm
-; CHECK-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
-; CHECK-NEXT: ldp d13, d12, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ldp d15, d14, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: addsvl sp, sp, #1
+; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x29, [sp, #64] // 8-byte Folded Reload
+; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload
; CHECK-NEXT: ret
%add = add <2 x i64> %a, ;
diff --git a/llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll b/llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
index 9d694523e09cd7b..011c3a4c25cacb7 100644
--- a/llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
+++ b/llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
@@ -120,7 +120,7 @@ define void @streaming_compatible_caller_and_callee() "aarch64_pstate_sm_compati
; Handle special cases here.
;
-define <2 x double> @streaming_compatible_with_neon_vectors(<2 x double> %arg) "aarch64_pstate_sm_compatible" nounwind #0 {
+define <2 x double> @streaming_compatible_with_neon_vectors(<2 x double> %arg) "aarch64_pstate_sm_compatible" nounwind {
; CHECK-LABEL: streaming_compatible_with_neon_vectors:
; CHECK: // %bb.0:
; CHECK-NEXT: stp d15, d14, [sp, #-96]! // 16-byte Folded Spill
@@ -166,7 +166,7 @@ define <2 x double> @streaming_compatible_with_neon_vectors(<2 x double> %arg) "
}
declare <2 x double> @normal_callee_vec_arg(<2 x double>)
-define @streaming_compatible_with_scalable_vectors( %arg) "aarch64_pstate_sm_compatible" nounwind #0 {
+define @streaming_compatible_with_scalable_vectors( %arg) "aarch64_pstate_sm_compatible" nounwind {
; CHECK-LABEL: streaming_compatible_with_scalable_vectors:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-32]! // 8-byte Folded Spill
@@ -258,7 +258,7 @@ define @streaming_compatible_with_scalable_vectors( @normal_callee_scalable_vec_arg()
-define @streaming_compatible_with_predicate_vectors( %arg) "aarch64_pstate_sm_compatible" nounwind #0 {
+define @streaming_compatible_with_predicate_vectors( %arg) "aarch64_pstate_sm_compatible" nounwind {
; CHECK-LABEL: streaming_compatible_with_predicate_vectors:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-32]! // 8-byte Folded Spill
@@ -436,6 +436,3 @@ define void @disable_tailcallopt() "aarch64_pstate_sm_compatible" nounwind {
tail call void @normal_callee();
ret void;
}
-
-
-attributes #0 = { nounwind "target-features"="+sve" }
diff --git a/llvm/test/CodeGen/AArch64/sme-streaming-interface.ll b/llvm/test/CodeGen/AArch64/sme-streaming-interface.ll
index 65521a0edc6d267..17b03716f068d26 100644
--- a/llvm/test/CodeGen/AArch64/sme-streaming-interface.ll
+++ b/llvm/test/CodeGen/AArch64/sme-streaming-interface.ll
@@ -147,7 +147,7 @@ define <4 x i32> @smstart_clobber_simdfp(<4 x i32> %x) nounwind {
}
; Ensure SVE registers are preserved correctly.
-define @smstart_clobber_sve( %x) #0 {
+define @smstart_clobber_sve( %x) nounwind {
; CHECK-LABEL: smstart_clobber_sve:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
@@ -224,7 +224,7 @@ define @smstart_clobber_sve( %x) #0 {
; Call streaming callee twice; there should be no spills/fills between the two
; calls since the registers should have already been clobbered.
-define @smstart_clobber_sve_duplicate( %x) #0 {
+define @smstart_clobber_sve_duplicate( %x) nounwind {
; CHECK-LABEL: smstart_clobber_sve_duplicate:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
@@ -360,7 +360,7 @@ define void @disable_tailcallopt() nounwind {
ret void;
}
-define i8 @call_to_non_streaming_pass_sve_objects(ptr nocapture noundef readnone %ptr) #1 {
+define i8 @call_to_non_streaming_pass_sve_objects(ptr nocapture noundef readnone %ptr) #0 {
; CHECK-LABEL: call_to_non_streaming_pass_sve_objects:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
@@ -405,5 +405,4 @@ declare i64 @llvm.aarch64.sme.cntsb()
declare void @foo(ptr noundef, ptr noundef, ptr noundef, i64 noundef)...
|
paulwalker-arm
approved these changes
Sep 12, 2023
MDevereau
approved these changes
Sep 12, 2023
ZijunZhaoCCK
pushed a commit
to ZijunZhaoCCK/llvm-project
that referenced
this pull request
Sep 19, 2023
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