[RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… #65283
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The tests are failed. |
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I have updated the CHECK statements in the test case. I had run the update_mca_test_checks script before rebasing which led to the failure. |
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…metic The intention of this test file long term is to test all valid (LMUL, SEW) pairs for each SchedWrite class. For this reason, we do not test every single instruction under every (LMUL, SEW) pair, since multiple instructions may use the same SchedWrite. For example, vadd.vv and vsub.vv both use the WriteVIALUV class. I didn't end up getting all (LMUL, SEW) pair for each SchedWrite class though. For example, vadd.vv and vadd.vx use WriteVIALUV and WriteVIALUX respectivley, but I treated all Vector Single-Width Integer Add and Subtract instructions as having the same behavior. I plan on improving the coverage as time goes on and figured this would be a good start. If there is any class of vector integer arithmetic instructions you'd like to see full coverage for in this patch, please let me know.
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wangpc-pp
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LGTM.
(maybe we should develop a test generator just like what we have in https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/rvv-intrinsic-generator?)
A test generator would be nice, although I think there are significantly less combinations compared to intrinsics. |
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llvm#65283) …metic The intention of this test file long term is to test all valid (LMUL, SEW) pairs for each SchedWrite class. For this reason, we do not test every single instruction under every (LMUL, SEW) pair, since multiple instructions may use the same SchedWrite. For example, vadd.vv and vsub.vv both use the WriteVIALUV class. I didn't end up getting all (LMUL, SEW) pair for each SchedWrite class though. For example, vadd.vv and vadd.vx use WriteVIALUV and WriteVIALUX respectivley, but I treated all Vector Single-Width Integer Add and Subtract instructions as having the same behavior. I plan on improving the coverage as time goes on and figured this would be a good start. If there is any class of vector integer arithmetic instructions you'd like to see full coverage for in this patch, please let me know.
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…metic
The intention of this test file long term is to test all valid (LMUL, SEW) pairs for each SchedWrite class. For this reason, we do not test every single instruction under every (LMUL, SEW) pair, since multiple instructions may use the same SchedWrite. For example, vadd.vv and vsub.vv both use the WriteVIALUV class.
I didn't end up getting all (LMUL, SEW) pair for each SchedWrite class though. For example, vadd.vv and vadd.vx use WriteVIALUV and WriteVIALUX respectivley, but I treated all Vector Single-Width Integer Add and Subtract instructions as having the same behavior. I plan on improving the coverage as time goes on and figured this would be a good start. If there is any class of vector integer arithmetic instructions you'd like to see full coverage for in this patch, please let me know.