[AArch64][GlobalISel] Look through COPY and G_BITCAST while selecting fcvtl2 (fpext) #65463
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| def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))), | ||
| (FCVTLv4i16 V64:$Rn)>; | ||
| def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn), | ||
| (i64 4)))), | ||
| (FCVTLv8i16 V128:$Rn)>; | ||
| def : Pat<(v2f64 (any_fpextend (v2f32 V64:$Rn))), | ||
| (FCVTLv2i32 V64:$Rn)>; | ||
| def : Pat<(v2f64 (any_fpextend (v2f32 (extract_high_v4f32 (v4f32 V128:$Rn))))), | ||
| def : PatIgnoreCopies<(v2f64 (any_fpextend (v2f32 (extract_high_v4f32 (v4f32 V128:$Rn))))), |
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Is this needed? Do you have a test case where it makes a difference?
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Sorry, I've mixed it up with another change.
| Root.getReg() == Extract->getOperand(1).getReg()) { | ||
| Register ExtReg = Extract->getOperand(2).getReg(); | ||
| auto Extract = getDefSrcRegIgnoringCopies(Root.getReg(), MRI); | ||
| while (Extract && Extract->MI->getOpcode() == TargetOpcode::G_BITCAST) |
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Does this work for big endian? I'm not sure if big endian works for global isel at the moment, but I would prefer not to introduce a lot of subtle cases that assume bitcast does not alter lane layout.
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Big endian currently doesn't work, we have known issues but you're right we should do a LE check here.
| return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}}; | ||
| } | ||
| } | ||
| if (Extract->MI->getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT) { |
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Why is every G_EXTRACT_VECTOR_ELT considered a high extract? Should it be checking that the Extract is a v2s64 and is extracting from index is 1?
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Thank you for the catch!
| auto LaneIdx = getIConstantVRegValWithLookThrough( | ||
| Extract->MI->getOperand(2).getReg(), MRI); | ||
| if (LaneIdx && | ||
| SrcTy == LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)) && |
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SrcTy == LLT::fixed_vector(2, 64) I think would work.
It tackles some regressions introduced in
https://reviews.llvm.org/D144670.