[mlir][LLVM] Model side effects of volatile and atomic load-store

[zero9178]

According to the LLVM language reference, both volatile memory operations and atomic operations (except unordered) do not simply read memory but also perform write operations on arbitrary memory[0][1].

In the case of volatile memory operations, this is the case due to the read possibly having target specific properties. A common real-world situation where this happens is reading memory mapped registers on an MCU for example. Atomic operations are more special. They form a kind of memory barrier which from the perspective of the optimizer/lang-ref makes writes from other threads visible in the current thread. Any kind of synchronization can therefore conservatively be modeled as a write-effect.

This PR therefore adjusts the side effects of llvm.load and llvm.store to add unknown global read and write effects if they are either atomic or volatile.

Regarding testing: I am not sure how to best test this change for llvm.store and the "globalness" of the effect that isn't just a unit test checking that the output matches exactly. For the time being, I added a test making sure that llvm.load does not get DCEd in aforementioned cases.

Related logic in LLVM proper:

llvm-project/llvm/lib/IR/Instruction.cpp

Lines 638 to 676 in 3398744

	bool Instruction::mayReadFromMemory() const {
	switch (getOpcode()) {
	default: return false;
	case Instruction::VAArg:
	case Instruction::Load:
	case Instruction::Fence: // FIXME: refine definition of mayReadFromMemory
	case Instruction::AtomicCmpXchg:
	case Instruction::AtomicRMW:
	case Instruction::CatchPad:
	case Instruction::CatchRet:
	return true;
	case Instruction::Call:
	case Instruction::Invoke:
	case Instruction::CallBr:
	return !cast<CallBase>(this)->onlyWritesMemory();
	case Instruction::Store:
	return !cast<StoreInst>(this)->isUnordered();
	}
	}
	bool Instruction::mayWriteToMemory() const {
	switch (getOpcode()) {
	default: return false;
	case Instruction::Fence: // FIXME: refine definition of mayWriteToMemory
	case Instruction::Store:
	case Instruction::VAArg:
	case Instruction::AtomicCmpXchg:
	case Instruction::AtomicRMW:
	case Instruction::CatchPad:
	case Instruction::CatchRet:
	return true;
	case Instruction::Call:
	case Instruction::Invoke:
	case Instruction::CallBr:
	return !cast<CallBase>(this)->onlyReadsMemory();
	case Instruction::Load:
	return !cast<LoadInst>(this)->isUnordered();
	}
	}

llvm-project/llvm/include/llvm/IR/Instructions.h

Lines 258 to 262 in 3398744

	bool isUnordered() const {
	return (getOrdering() == AtomicOrdering::NotAtomic ||
	getOrdering() == AtomicOrdering::Unordered) &&
	!isVolatile();
	}

[0] https://llvm.org/docs/LangRef.html#volatile-memory-accesses
[1] https://llvm.org/docs/Atomics.html#monotonic

[gysit]

LGTM!

Adding a short comments that explain the additional effects would be nice!