[RISCV] Make InitUndef handle undef operand #65755

BeMg · 2023-09-08T13:22:06Z

When operand be mark as undef, the InitUndef will miss this case.

This patch

support the undef operand case
Merge the code for handleImplictDef and fixupUndefOperandOnly to reduce the searching logic.

lukel97 · 2023-09-08T13:44:56Z

Hi, if it's of any use to you I reduced the test case last night with llvm-reduce:

target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v16i8(<vscale x 8 x i8>, <16 x i8>, i64 immarg) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64, i64 immarg) #1

define void @foo(<vscale x 8 x i8> %0) #2 {
  %2 = tail call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v16i8(<vscale x 8 x i8> undef, <16 x i8> undef, i64 0)
  %3 = tail call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v16i8(<vscale x 8 x i8> undef, <16 x i8> poison, i64 0)
  br label %4

4:                                                ; preds = %4, %1
  %5 = tail call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> %2, i64 0, i64 0, i64 0)
  %6 = tail call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %5, i64 0)
  %7 = bitcast <16 x i8> %6 to <2 x i64>
  %8 = extractelement <2 x i64> %7, i64 0
  %9 = insertvalue [2 x i64] zeroinitializer, i64 %8, 0
  %10 = tail call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %3, i64 0, i64 0, i64 0)
  %11 = tail call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %10, i64 0)
  %12 = bitcast <16 x i8> %11 to <2 x i64>
  %13 = extractelement <2 x i64> %12, i64 0
  %14 = insertvalue [2 x i64] zeroinitializer, i64 %13, 0
  %15 = tail call fastcc [2 x i64] null([2 x i64] %9, [2 x i64] %14, [2 x i64] zeroinitializer)
  br label %4
}

attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
attributes #2 = { "target-features"="+64bit,+a,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-c,-e,-h,-save-restore,-svinval,-svnapot,-svpbmt,-unaligned-scalar-mem,-unaligned-vector-mem,-xcvalu,-xcvbi,-xcvbitmanip,-xcvmac,-xcvsimd,-xsfcie,-xsfvcp,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvfh,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }

BeMg · 2023-09-11T06:02:43Z

Hi, if it's of any use to you I reduced the test case last night with llvm-reduce:

target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v16i8(<vscale x 8 x i8>, <16 x i8>, i64 immarg) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64, i64 immarg) #1

define void @foo(<vscale x 8 x i8> %0) #2 {
  %2 = tail call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v16i8(<vscale x 8 x i8> undef, <16 x i8> undef, i64 0)
  %3 = tail call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v16i8(<vscale x 8 x i8> undef, <16 x i8> poison, i64 0)
  br label %4

4:                                                ; preds = %4, %1
  %5 = tail call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> %2, i64 0, i64 0, i64 0)
  %6 = tail call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %5, i64 0)
  %7 = bitcast <16 x i8> %6 to <2 x i64>
  %8 = extractelement <2 x i64> %7, i64 0
  %9 = insertvalue [2 x i64] zeroinitializer, i64 %8, 0
  %10 = tail call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %3, i64 0, i64 0, i64 0)
  %11 = tail call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %10, i64 0)
  %12 = bitcast <16 x i8> %11 to <2 x i64>
  %13 = extractelement <2 x i64> %12, i64 0
  %14 = insertvalue [2 x i64] zeroinitializer, i64 %13, 0
  %15 = tail call fastcc [2 x i64] null([2 x i64] %9, [2 x i64] %14, [2 x i64] zeroinitializer)
  br label %4
}

attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
attributes #2 = { "target-features"="+64bit,+a,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-c,-e,-h,-save-restore,-svinval,-svnapot,-svpbmt,-unaligned-scalar-mem,-unaligned-vector-mem,-xcvalu,-xcvbi,-xcvbitmanip,-xcvmac,-xcvsimd,-xsfcie,-xsfvcp,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvfh,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }

Thanks, very helpful!

BeMg · 2023-09-11T12:09:06Z

Use the reduce version testcase

topperc · 2023-09-16T21:01:49Z

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

+      continue;
+    if (!isVectorRegClass(UseMO.getReg()))
+      continue;
+    if (UseMO.getReg() == 0)


We already checked it is virtual. It can't be virtual and 0 can it?

You're right. $noreg is not belong to virtual register.

Remove the reg == 0 .

topperc · 2023-09-16T21:02:24Z

llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll

+; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+m,+zfh,+zvfh \
+; RUN:  < %s | FileCheck %s
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)


Drop Function Attrs comments

topperc · 2023-09-16T21:02:40Z

llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll

+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v4i32(<vscale x 2 x i32>, <4 x i32>, i64 immarg) #3
+
+define void @foo(<vscale x 8 x i8> %0) #2 {


#2 doesn't exist. You can remove it

BeMg · 2023-10-11T06:02:36Z

ping

topperc

LGTM

Bug report from llvm#65704. The InitUndef pass miss the pattern that operand is not implict_def but undef directly. This patch support this pattern in InitUndef pass.

They share the same pattern of replacing the Operand with PseudoRVVInitUndef. This patch 1. reduces the logic for finding MachineInstr that needs to be fixed. 2. emit PseudoRVVInitUndef just before the user's operand to reduce register pressure (shorter LiveInterval).

BeMg requested a review from a team as a code owner September 8, 2023 13:22

github-actions bot added the backend:RISC-V label Sep 8, 2023

BeMg force-pushed the Undef-Init-Fix branch from a8ae179 to 4fc6b04 Compare September 11, 2023 12:08

topperc reviewed Sep 16, 2023

View reviewed changes

BeMg requested a review from topperc September 18, 2023 03:52

topperc approved these changes Nov 29, 2023

View reviewed changes

BeMg force-pushed the Undef-Init-Fix branch from 3877829 to 146bfc6 Compare December 1, 2023 05:29

BeMg added 6 commits November 30, 2023 21:42

[RISCV][NFC] precommit for 65704

8f67d4b

[RISCV] InitUndef also handle undef

a2bee1c

Bug report from llvm#65704. The InitUndef pass miss the pattern that operand is not implict_def but undef directly. This patch support this pattern in InitUndef pass.

Remove the (reg == 0) because it already to be checked by isVirtrual

65b6192

Enhence the testcase by remove func attr

ea04b3b

Update testcase after rebase

60b0a5c

BeMg force-pushed the Undef-Init-Fix branch from 146bfc6 to 60b0a5c Compare December 1, 2023 05:49

BeMg merged commit 5ecb37b into llvm:main Dec 1, 2023
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[RISCV] Make InitUndef handle undef operand #65755

[RISCV] Make InitUndef handle undef operand #65755

BeMg commented Sep 8, 2023

lukel97 commented Sep 8, 2023

BeMg commented Sep 11, 2023

BeMg commented Sep 11, 2023

topperc Sep 16, 2023

BeMg Sep 18, 2023

topperc Sep 16, 2023

BeMg Sep 18, 2023

topperc Sep 16, 2023

BeMg Sep 18, 2023

BeMg commented Oct 11, 2023

topperc left a comment

[RISCV] Make InitUndef handle undef operand #65755

[RISCV] Make InitUndef handle undef operand #65755

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BeMg commented Sep 8, 2023

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