[ARM][ISel] Fix crash of ISD::FMINNUM/FMAXNUM

[vfdff]

The instruction of ISD::FMINNUM/FMAXNUM should be legal if HasFPARMv8 && HasNEON.
For the combination of armv7+fp-armv8, armv7 imply the feature HasNEON
on, and fp-armv8 matchs the feature HasFPARMv8, so it is legal

Fixes #65820

[davemgreen]

I think it should be the other way around. The instruction should be legal if HasFPARMv8 && HasNEON. It's a bit of a strange combination to have armv7+fp-armv8, but that appears to be what happens for the scalar instructions and from gcc.

[vfdff]

I think it should be the other way around. The instruction should be legal if HasFPARMv8 && HasNEON. It's a bit of a strange combination to have armv7+fp-armv8, but that appears to be what happens for the scalar instructions and from gcc.

Thanks @davemgreen. Would you please show how can we infer that the instruction fmaxnum should be legal if HasFPARMv8 && HasNEON ?
The related pattern is defined with Requires<[HasV8, HasNEON]>, so the instruction should be legal iff HasV8 && HasNEON. Meanwhile, the feature HasV8 and HasFPARMv8 is independent from the definition of ARMv8a.

def NEON_VMAXNMNQf  : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
                                  N3RegFrm, NoItinerary, "vmaxnm", "f32",
                                  v4f32, v4f32, fmaxnum, 1>,
                                  Requires<[HasV8, HasNEON]>;

def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
                                                       FeatureFPARMv8,
                                                       FeatureNEON,
                                                       ...]

[davemgreen]

Yeah can we change it to [HasFPARMv8, HasNEON]?

[vfdff]

Yeah can we change it to [HasFPARMv8, HasNEON]?
Apply your comment, thanks!

[davemgreen]

Other than the comments, this LGTM. Thanks for working on this.

[davemgreen]

Thanks. Some of the tests are showing some worse scalization but for what you are fixing this LGTM. Thanks for the fix.