[AArch64][GlobalISel] Add lowering for constant BIT/BIF/BSP #65897
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
aemerson
reviewed
Sep 10, 2023
| @@ -216,7 +216,7 @@ def G_PREFETCH : AArch64GenericInstruction { | |||
| } | |||
|
|
|||
| // Generic bitwise insert if true. | |||
| @@ -216,7 +216,7 @@ def G_PREFETCH : AArch64GenericInstruction { | |||
| } | |||
|
|
|||
| // Generic bitwise insert if true. | |||
| def G_BIT : AArch64GenericInstruction { | |||
| def G_BSP : AArch64GenericInstruction { | |||
There was a problem hiding this comment.
And this opcode needs a bit of documentation since it's not a real AArch64 instruction.
Comment on lines
347
to
356
| MachineInstr *LHS = | ||
| getOpcodeDef(TargetOpcode::G_AND, MI.getOperand(1).getReg(), MRI); | ||
| MachineInstr *RHS = | ||
| getOpcodeDef(TargetOpcode::G_AND, MI.getOperand(2).getReg(), MRI); | ||
| if (!LHS || !RHS) | ||
| return false; | ||
|
|
||
| auto *BV1 = getOpcodeDef<GBuildVector>(LHS->getOperand(2).getReg(), MRI); | ||
| auto *BV2 = getOpcodeDef<GBuildVector>(RHS->getOperand(2).getReg(), MRI); | ||
| if (!BV1 || !BV2) | ||
| return false; |
There was a problem hiding this comment.
At least some of this could be done with mi_match()? Not a big deal either way.
Comment on lines
369
to
371
| std::get<0>(MatchInfo) = LHS->getOperand(1).getReg(); | ||
| std::get<1>(MatchInfo) = RHS->getOperand(1).getReg(); | ||
| std::get<2>(MatchInfo) = RHS->getOperand(2).getReg(); |
There was a problem hiding this comment.
I think you can just do MatchInfo = {v1,v2,v3};
Comment on lines
359
to
361
| for (int k = 0; k < DstTy.getNumElements(); k++) { | ||
| auto ValAndVReg1 = getIConstantVRegValWithLookThrough( | ||
| BV1->getOperand(k + 1).getReg(), MRI); |
There was a problem hiding this comment.
You can use GBuildVector::getSourceReg(k).
tschuett
reviewed
Sep 10, 2023
| auto ValAndVReg2 = getIConstantVRegValWithLookThrough( | ||
| BV2->getOperand(k + 1).getReg(), MRI); | ||
| if (!ValAndVReg1 || !ValAndVReg2 || | ||
| ValAndVReg1->Value != ~ValAndVReg2->Value) |
There was a problem hiding this comment.
I prefer *ValAndReg1 for ValAndReg2 precedence is not obvious.
tschuett
reviewed
Sep 10, 2023
| if (!BV1 || !BV2) | ||
| return false; | ||
|
|
||
| for (int k = 0; k < DstTy.getNumElements(); k++) { |
There was a problem hiding this comment.
for (int k = 0, int NumElements = DstTy.getNumElements(); k < NumElements; ++k)
There was a problem hiding this comment.
In the far future a scalable vector might sneak in, then you cannot walk over its members.
The non-constant versions already work through tablegen patters, this mirrors the basic support for or(and(X, C), and(Y, ~C)) from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
davemgreen
force-pushed
the
gh-gi-bsp
branch
from
2df1802
to
ff25643
Compare
|
Hi @davemgreen, I am seeing flang/clang failures in the llvm-test-suite after this patch with tests involving copy sign:
Can you check if this is related to your patch that involves copy sign on aarch64? |
|
Hello. It sounds like it might be related. I might not have updated the existing copysign code correctly, as I was planning to remove it eventually. I will revert and take a look. |
davemgreen
added a commit
that referenced
this pull request
Sep 17, 2023
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
ZijunZhaoCCK
pushed a commit
to ZijunZhaoCCK/llvm-project
that referenced
this pull request
Sep 19, 2023
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
ZijunZhaoCCK
pushed a commit
to ZijunZhaoCCK/llvm-project
that referenced
this pull request
Sep 19, 2023
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
zahiraam
pushed a commit
to tahonermann/llvm-project
that referenced
this pull request
Oct 24, 2023
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
zahiraam
pushed a commit
to tahonermann/llvm-project
that referenced
this pull request
Oct 24, 2023
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
I have been making my way through GlobalISel vector fp, making sure all the basic types are currently working. In looking at fcopysign I managed to rewrite it in a way that we just widen to vectors, as opposed to relying on custom lowering. That misses handling vector constants (which Mark here is currently looking at) and transforming
or/andintobit.The non-constant bit/bif/bsp already work through tablegen patters, this patch handles the constant case, mirroring the basic support for
or(and(X, C), and(Y, ~C))from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.