[AArch64] Remove the Z#_HI register definitions #66353
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pawosm-arm
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fhahn,
paulwalker-arm and
DanielKristofKiss
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@llvm/pr-subscribers-backend-aarch64 @llvm/pr-subscribers-llvm-globalisel ChangesThe Z#_HI register definitions were created during the very early SVE enablement work and before the SVE calling convention was locked in.As they look entirely unused, they need to go.Patch is 70.86 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66353.diff 14 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 18fc8c77a0e44d9..387620510aa1778 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -31,10 +31,6 @@ let Namespace = "AArch64" in {
def subo64 : SubRegIndex<64>;
// SVE
def zsub : SubRegIndex<128>;
- // Note: zsub_hi should never be used directly because it represents
- // the scalable part of the SVE vector and cannot be manipulated as a
- // subvector in the same way the lower 128bits can.
- def zsub_hi : SubRegIndex<128>;
// Note: Code depends on these having consecutive numbers
def dsub0 : SubRegIndex<64>;
def dsub1 : SubRegIndex<64>;
@@ -785,75 +781,40 @@ def P13 : AArch64Reg<13, "p13">, DwarfRegNum<[61]>;
def P14 : AArch64Reg<14, "p14">, DwarfRegNum<[62]>;
def P15 : AArch64Reg<15, "p15">, DwarfRegNum<[63]>;
-// The part of SVE registers that don't overlap Neon registers.
-// These are only used as part of clobber lists.
-def Z0_HI : AArch64Reg<0, "z0_hi">;
-def Z1_HI : AArch64Reg<1, "z1_hi">;
-def Z2_HI : AArch64Reg<2, "z2_hi">;
-def Z3_HI : AArch64Reg<3, "z3_hi">;
-def Z4_HI : AArch64Reg<4, "z4_hi">;
-def Z5_HI : AArch64Reg<5, "z5_hi">;
-def Z6_HI : AArch64Reg<6, "z6_hi">;
-def Z7_HI : AArch64Reg<7, "z7_hi">;
-def Z8_HI : AArch64Reg<8, "z8_hi">;
-def Z9_HI : AArch64Reg<9, "z9_hi">;
-def Z10_HI : AArch64Reg<10, "z10_hi">;
-def Z11_HI : AArch64Reg<11, "z11_hi">;
-def Z12_HI : AArch64Reg<12, "z12_hi">;
-def Z13_HI : AArch64Reg<13, "z13_hi">;
-def Z14_HI : AArch64Reg<14, "z14_hi">;
-def Z15_HI : AArch64Reg<15, "z15_hi">;
-def Z16_HI : AArch64Reg<16, "z16_hi">;
-def Z17_HI : AArch64Reg<17, "z17_hi">;
-def Z18_HI : AArch64Reg<18, "z18_hi">;
-def Z19_HI : AArch64Reg<19, "z19_hi">;
-def Z20_HI : AArch64Reg<20, "z20_hi">;
-def Z21_HI : AArch64Reg<21, "z21_hi">;
-def Z22_HI : AArch64Reg<22, "z22_hi">;
-def Z23_HI : AArch64Reg<23, "z23_hi">;
-def Z24_HI : AArch64Reg<24, "z24_hi">;
-def Z25_HI : AArch64Reg<25, "z25_hi">;
-def Z26_HI : AArch64Reg<26, "z26_hi">;
-def Z27_HI : AArch64Reg<27, "z27_hi">;
-def Z28_HI : AArch64Reg<28, "z28_hi">;
-def Z29_HI : AArch64Reg<29, "z29_hi">;
-def Z30_HI : AArch64Reg<30, "z30_hi">;
-def Z31_HI : AArch64Reg<31, "z31_hi">;
-
// SVE variable-size vector registers
-let SubRegIndices = [zsub,zsub_hi] in {
-def Z0 : AArch64Reg<0, "z0", [Q0, Z0_HI]>, DwarfRegNum<[96]>;
-def Z1 : AArch64Reg<1, "z1", [Q1, Z1_HI]>, DwarfRegNum<[97]>;
-def Z2 : AArch64Reg<2, "z2", [Q2, Z2_HI]>, DwarfRegNum<[98]>;
-def Z3 : AArch64Reg<3, "z3", [Q3, Z3_HI]>, DwarfRegNum<[99]>;
-def Z4 : AArch64Reg<4, "z4", [Q4, Z4_HI]>, DwarfRegNum<[100]>;
-def Z5 : AArch64Reg<5, "z5", [Q5, Z5_HI]>, DwarfRegNum<[101]>;
-def Z6 : AArch64Reg<6, "z6", [Q6, Z6_HI]>, DwarfRegNum<[102]>;
-def Z7 : AArch64Reg<7, "z7", [Q7, Z7_HI]>, DwarfRegNum<[103]>;
-def Z8 : AArch64Reg<8, "z8", [Q8, Z8_HI]>, DwarfRegNum<[104]>;
-def Z9 : AArch64Reg<9, "z9", [Q9, Z9_HI]>, DwarfRegNum<[105]>;
-def Z10 : AArch64Reg<10, "z10", [Q10, Z10_HI]>, DwarfRegNum<[106]>;
-def Z11 : AArch64Reg<11, "z11", [Q11, Z11_HI]>, DwarfRegNum<[107]>;
-def Z12 : AArch64Reg<12, "z12", [Q12, Z12_HI]>, DwarfRegNum<[108]>;
-def Z13 : AArch64Reg<13, "z13", [Q13, Z13_HI]>, DwarfRegNum<[109]>;
-def Z14 : AArch64Reg<14, "z14", [Q14, Z14_HI]>, DwarfRegNum<[110]>;
-def Z15 : AArch64Reg<15, "z15", [Q15, Z15_HI]>, DwarfRegNum<[111]>;
-def Z16 : AArch64Reg<16, "z16", [Q16, Z16_HI]>, DwarfRegNum<[112]>;
-def Z17 : AArch64Reg<17, "z17", [Q17, Z17_HI]>, DwarfRegNum<[113]>;
-def Z18 : AArch64Reg<18, "z18", [Q18, Z18_HI]>, DwarfRegNum<[114]>;
-def Z19 : AArch64Reg<19, "z19", [Q19, Z19_HI]>, DwarfRegNum<[115]>;
-def Z20 : AArch64Reg<20, "z20", [Q20, Z20_HI]>, DwarfRegNum<[116]>;
-def Z21 : AArch64Reg<21, "z21", [Q21, Z21_HI]>, DwarfRegNum<[117]>;
-def Z22 : AArch64Reg<22, "z22", [Q22, Z22_HI]>, DwarfRegNum<[118]>;
-def Z23 : AArch64Reg<23, "z23", [Q23, Z23_HI]>, DwarfRegNum<[119]>;
-def Z24 : AArch64Reg<24, "z24", [Q24, Z24_HI]>, DwarfRegNum<[120]>;
-def Z25 : AArch64Reg<25, "z25", [Q25, Z25_HI]>, DwarfRegNum<[121]>;
-def Z26 : AArch64Reg<26, "z26", [Q26, Z26_HI]>, DwarfRegNum<[122]>;
-def Z27 : AArch64Reg<27, "z27", [Q27, Z27_HI]>, DwarfRegNum<[123]>;
-def Z28 : AArch64Reg<28, "z28", [Q28, Z28_HI]>, DwarfRegNum<[124]>;
-def Z29 : AArch64Reg<29, "z29", [Q29, Z29_HI]>, DwarfRegNum<[125]>;
-def Z30 : AArch64Reg<30, "z30", [Q30, Z30_HI]>, DwarfRegNum<[126]>;
-def Z31 : AArch64Reg<31, "z31", [Q31, Z31_HI]>, DwarfRegNum<[127]>;
+let SubRegIndices = [zsub] in {
+def Z0 : AArch64Reg<0, "z0", [Q0]>, DwarfRegNum<[96]>;
+def Z1 : AArch64Reg<1, "z1", [Q1]>, DwarfRegNum<[97]>;
+def Z2 : AArch64Reg<2, "z2", [Q2]>, DwarfRegNum<[98]>;
+def Z3 : AArch64Reg<3, "z3", [Q3]>, DwarfRegNum<[99]>;
+def Z4 : AArch64Reg<4, "z4", [Q4]>, DwarfRegNum<[100]>;
+def Z5 : AArch64Reg<5, "z5", [Q5]>, DwarfRegNum<[101]>;
+def Z6 : AArch64Reg<6, "z6", [Q6]>, DwarfRegNum<[102]>;
+def Z7 : AArch64Reg<7, "z7", [Q7]>, DwarfRegNum<[103]>;
+def Z8 : AArch64Reg<8, "z8", [Q8]>, DwarfRegNum<[104]>;
+def Z9 : AArch64Reg<9, "z9", [Q9]>, DwarfRegNum<[105]>;
+def Z10 : AArch64Reg<10, "z10", [Q10]>, DwarfRegNum<[106]>;
+def Z11 : AArch64Reg<11, "z11", [Q11]>, DwarfRegNum<[107]>;
+def Z12 : AArch64Reg<12, "z12", [Q12]>, DwarfRegNum<[108]>;
+def Z13 : AArch64Reg<13, "z13", [Q13]>, DwarfRegNum<[109]>;
+def Z14 : AArch64Reg<14, "z14", [Q14]>, DwarfRegNum<[110]>;
+def Z15 : AArch64Reg<15, "z15", [Q15]>, DwarfRegNum<[111]>;
+def Z16 : AArch64Reg<16, "z16", [Q16]>, DwarfRegNum<[112]>;
+def Z17 : AArch64Reg<17, "z17", [Q17]>, DwarfRegNum<[113]>;
+def Z18 : AArch64Reg<18, "z18", [Q18]>, DwarfRegNum<[114]>;
+def Z19 : AArch64Reg<19, "z19", [Q19]>, DwarfRegNum<[115]>;
+def Z20 : AArch64Reg<20, "z20", [Q20]>, DwarfRegNum<[116]>;
+def Z21 : AArch64Reg<21, "z21", [Q21]>, DwarfRegNum<[117]>;
+def Z22 : AArch64Reg<22, "z22", [Q22]>, DwarfRegNum<[118]>;
+def Z23 : AArch64Reg<23, "z23", [Q23]>, DwarfRegNum<[119]>;
+def Z24 : AArch64Reg<24, "z24", [Q24]>, DwarfRegNum<[120]>;
+def Z25 : AArch64Reg<25, "z25", [Q25]>, DwarfRegNum<[121]>;
+def Z26 : AArch64Reg<26, "z26", [Q26]>, DwarfRegNum<[122]>;
+def Z27 : AArch64Reg<27, "z27", [Q27]>, DwarfRegNum<[123]>;
+def Z28 : AArch64Reg<28, "z28", [Q28]>, DwarfRegNum<[124]>;
+def Z29 : AArch64Reg<29, "z29", [Q29]>, DwarfRegNum<[125]>;
+def Z30 : AArch64Reg<30, "z30", [Q30]>, DwarfRegNum<[126]>;
+def Z31 : AArch64Reg<31, "z31", [Q31]>, DwarfRegNum<[127]>;
}
// Enum describing the element size for destructive
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
index a6133bd898681cf..d2e94b29fe0e3af 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
@@ -68,19 +68,19 @@ define i32 @test_musttail_variadic_spill(i32 %arg0, ...) {
; CHECK-NEXT: stp q3, q2, [sp, #64] ; 32-byte Folded Spill
; CHECK-NEXT: stp q1, q0, [sp, #96] ; 32-byte Folded Spill
; CHECK-NEXT: bl _puts
-; CHECK-NEXT: ldp q1, q0, [sp, #96] ; 32-byte Folded Reload
; CHECK-NEXT: mov w0, w19
-; CHECK-NEXT: ldp q3, q2, [sp, #64] ; 32-byte Folded Reload
; CHECK-NEXT: mov x1, x20
-; CHECK-NEXT: ldp q5, q4, [sp, #32] ; 32-byte Folded Reload
; CHECK-NEXT: mov x2, x21
-; CHECK-NEXT: ldp q7, q6, [sp] ; 32-byte Folded Reload
; CHECK-NEXT: mov x3, x22
; CHECK-NEXT: mov x4, x23
; CHECK-NEXT: mov x5, x24
; CHECK-NEXT: mov x6, x25
; CHECK-NEXT: mov x7, x26
; CHECK-NEXT: mov x8, x27
+; CHECK-NEXT: ldp q1, q0, [sp, #96] ; 32-byte Folded Reload
+; CHECK-NEXT: ldp q3, q2, [sp, #64] ; 32-byte Folded Reload
+; CHECK-NEXT: ldp q5, q4, [sp, #32] ; 32-byte Folded Reload
+; CHECK-NEXT: ldp q7, q6, [sp] ; 32-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #208] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #192] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #176] ; 16-byte Folded Reload
@@ -140,19 +140,19 @@ define void @f_thunk(ptr %this, ...) {
; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: bl _get_f
; CHECK-NEXT: mov x9, x0
-; CHECK-NEXT: ldp q1, q0, [sp, #96] ; 32-byte Folded Reload
-; CHECK-NEXT: ldp q3, q2, [sp, #64] ; 32-byte Folded Reload
; CHECK-NEXT: mov x0, x19
-; CHECK-NEXT: ldp q5, q4, [sp, #32] ; 32-byte Folded Reload
; CHECK-NEXT: mov x1, x20
-; CHECK-NEXT: ldp q7, q6, [sp] ; 32-byte Folded Reload
; CHECK-NEXT: mov x2, x21
; CHECK-NEXT: mov x3, x22
; CHECK-NEXT: mov x4, x23
; CHECK-NEXT: mov x5, x24
; CHECK-NEXT: mov x6, x25
; CHECK-NEXT: mov x7, x26
+; CHECK-NEXT: ldp q1, q0, [sp, #96] ; 32-byte Folded Reload
; CHECK-NEXT: mov x8, x27
+; CHECK-NEXT: ldp q3, q2, [sp, #64] ; 32-byte Folded Reload
+; CHECK-NEXT: ldp q5, q4, [sp, #32] ; 32-byte Folded Reload
+; CHECK-NEXT: ldp q7, q6, [sp] ; 32-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #240] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x20, x19, [sp, #224] ; 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #208] ; 16-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/machine-cp-clobbers.mir b/llvm/test/CodeGen/AArch64/machine-cp-clobbers.mir
index bea332e84ca4760..324cce26d15b89c 100644
--- a/llvm/test/CodeGen/AArch64/machine-cp-clobbers.mir
+++ b/llvm/test/CodeGen/AArch64/machine-cp-clobbers.mir
@@ -32,8 +32,8 @@ body: |
bb.0:
; CHECK-LABEL: name: dont_propagate_past_upper_subreg_kill
; CHECK: HINT 0, implicit-def $z0
- ; CHECK: HINT 0, implicit-def $z1_hi
- ; CHECK: HINT 0, implicit killed $z1_hi
+ ; CHECK: HINT 0, implicit-def $q1
+ ; CHECK: HINT 0, implicit killed $q1
; CHECK: $z1 = COPY killed $z0
; CHECK: $z2 = COPY $z1
; CHECK: HINT 0, implicit $z2
@@ -41,8 +41,8 @@ body: |
$z1 = COPY killed $z0
$z0 = COPY killed $z1
- HINT 0, implicit-def $z1_hi
- HINT 0, implicit killed $z1_hi
+ HINT 0, implicit-def $q1
+ HINT 0, implicit killed $q1
$z1 = COPY killed $z0
$z2 = COPY $z1
diff --git a/llvm/test/CodeGen/AArch64/preserve.ll b/llvm/test/CodeGen/AArch64/preserve.ll
index 924e6f8487ebf0b..2e8568a31640e1f 100644
--- a/llvm/test/CodeGen/AArch64/preserve.ll
+++ b/llvm/test/CodeGen/AArch64/preserve.ll
@@ -4,13 +4,13 @@
target triple = "aarch64-unknown-unknown"
declare void @bar1()
define preserve_mostcc void @baz() #0 {
-; CHECK: baz Clobbered Registers: $ffr $fpcr $nzcv $sp $vg $wsp $za $b0 $b1 $b2 $b3 $b4 $b5 $b6 $b7 $b16 $b17 $b18 $b19 $b20 $b21 $b22 $b23 $b24 $b25 $b26 $b27 $b28 $b29 $b30 $b31 $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $h0 $h1 $h2 $h3 $h4 $h5 $h6 $h7 $h16 $h17 $h18 $h19 $h20 $h21 $h22 $h23 $h24 $h25 $h26 $h27 $h28 $h29 $h30 $h31 $p0 $p1 $p2 $p3 $p4 $p5 $p6 $p7 $p8 $p9 $p10 $p11 $p12 $p13 $p14 $p15 $q0 $q1 $q2 $q3 $q4 $q5 $q6 $q7 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $q16 $q17 $q18 $q19 $q20 $q21 $q22 $q23 $q24 $q25 $q26 $q27 $q28 $q29 $q30 $q31 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 $s28 $s29 $s30 $s31 $w0 $w1 $w2 $w3 $w4 $w5 $w6 $w7 $w8 $w16 $w17 $w18 $x0 $x1 $x2 $x3 $x4 $x5 $x6 $x7 $x8 $x16 $x17 $x18 $z0 $z1 $z2 $z3 $z4 $z5 $z6 $z7 $z8 $z9 $z10 $z11 $z12 $z13 $z14 $z15 $z16 $z17 $z18 $z19 $z20 $z21 $z22 $z23 $z24 $z25 $z26 $z27 $z28 $z29 $z30 $z31 $zab0 $zad0 $zad1 $zad2 $zad3 $zad4 $zad5 $zad6 $zad7 $zah0 $zah1 $zaq0 $zaq1 $zaq2 $zaq3 $zaq4 $zaq5 $zaq6 $zaq7 $zaq8 $zaq9 $zaq10 $zaq11 $zaq12 $zaq13 $zaq14 $zaq15 $zas0 $zas1 $zas2 $zas3 $zt0 $z0_hi $z1_hi $z2_hi $z3_hi $z4_hi $z5_hi $z6_hi $z7_hi $z8_hi $z9_hi $z10_hi $z11_hi $z12_hi $z13_hi $z14_hi $z15_hi $z16_hi $z17_hi $z18_hi $z19_hi $z20_hi $z21_hi $z22_hi $z23_hi $z24_hi $z25_hi $z26_hi $z27_hi $z28_hi $z29_hi $z30_hi $z31_hi $d0_d1 $d1_d2 $d2_d3 $d3_d4 $d4_d5 $d5_d6 $d6_d7 $d7_d8 $d15_d16 $d16_d17 $d17_d18 $d18_d19 $d19_d20 $d20_d21 $d21_d22 $d22_d23 $d23_d24 $d24_d25 $d25_d26 $d26_d27 $d27_d28 $d28_d29 $d29_d30 $d30_d31 $d31_d0 $d0_d1_d2_d3 $d1_d2_d3_d4 $d2_d3_d4_d5 $d3_d4_d5_d6 $d4_d5_d6_d7 $d5_d6_d7_d8 $d6_d7_d8_d9 $d7_d8_d9_d10 $d13_d14_d15_d16 $d14_d15_d16_d17 $d15_d16_d17_d18 $d16_d17_d18_d19 $d17_d18_d19_d20 $d18_d19_d20_d21 $d19_d20_d21_d22 $d20_d21_d22_d23 $d21_d22_d23_d24 $d22_d23_d24_d25 $d23_d24_d25_d26 $d24_d25_d26_d27 $d25_d26_d27_d28 $d26_d27_d28_d29 $d27_d28_d29_d30 $d28_d29_d30_d31 $d29_d30_d31_d0 $d30_d31_d0_d1 $d31_d0_d1_d2 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d30_d31_d0 $d31_d0_d1 $p0_p1 $p1_p2 $p2_p3 $p3_p4 $p4_p5 $p5_p6 $p6_p7 $p7_p8 $p8_p9 $p9_p10 $p10_p11 $p11_p12 $p12_p13 $p13_p14 $p14_p15 $p15_p0 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q4_q5 $q5_q6 $q6_q7 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q15_q16 $q16_q17 $q17_q18 $q18_q19 $q19_q20 $q20_q21 $q21_q22 $q22_q23 $q23_q24 $q24_q25 $q25_q26 $q26_q27 $q27_q28 $q28_q29 $q29_q30 $q30_q31 $q31_q0 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q4_q5_q6_q7 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $q13_q14_q15_q16 $q14_q15_q16_q17 $q15_q16_q17_q18 $q16_q17_q18_q19 $q17_q18_q19_q20 $q18_q19_q20_q21 $q19_q20_q21_q22 $q20_q21_q22_q23 $q21_q22_q23_q24 $q22_q23_q24_q25 $q23_q24_q25_q26 $q24_q25_q26_q27 $q25_q26_q27_q28 $q26_q27_q28_q29 $q27_q28_q29_q30 $q28_q29_q30_q31 $q29_q30_q31_q0 $q30_q31_q0_q1 $q31_q0_q1_q2 $q0_q1_q2 $q1_q2_q3 $q2_q3_q4 $q3_q4_q5 $q4_q5_q6 $q5_q6_q7 $q6_q7_q8 $q7_q8_q9 $q8_q9_q10 $q9_q10_q11 $q10_q11_q12 $q11_q12_q13 $q12_q13_q14 $q13_q14_q15 $q14_q15_q16 $q15_q16_q17 $q16_q17_q18 $q17_q18_q19 $q18_q19_q20 $q19_q20_q21 $q20_q21_q22 $q21_q22_q23 $q22_q23_q24 $q23_q24_q25 $q24_q25_q26 $q25_q26_q27 $q26_q27_q28 $q27_q28_q29 $q28_q29_q30 $q29_q30_q31 $q30_q31_q0 $q31_q0_q1 $x0_x1_x2_x3_x4_x5_x6_x7 $x2_x3_x4_x5_x6_x7_x8_x9 $x4_x5_x6_x7_x8_x9_x10_x11 $x6_x7_x8_x9_x10_x11_x12_x13 $x8_x9_x10_x11_x12_x13_x14_x15 $x10_x11_x12_x13_x14_x15_x16_x17 $x12_x13_x14_x15_x16_x17_x18_x19 $x14_x15_x16_x17_x18_x19_x20_x21 $x16_x17_x18_x19_x20_x21_x22_x23 $x18_x19_x20_x21_x22_x23_x24_x25 $w30_wzr $w0_w1 $w2_w3 $w4_w5 $w6_w7 $w8_w9 $w10_w11 $w12_w13 $w14_w15 $w16_w17 $w18_w19 $lr_xzr $x0_x1 $x2_x3 $x4_x5 $x6_x7 $x8_x9 $x10_x11 $x12_x13 $x14_x15 $x16_x17 $x18_x19 $z0_z1 $z1_z2 $z2_z3 $z3_z4 $z4_z5 $z5_z6 $z6...
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paulwalker-arm
approved these changes
Sep 14, 2023
pawosm-arm
changed the title
The Z#_HI register definitions were created during the very early SVE enablement work and before the SVE calling convention was locked in. As they look entirely unused, they need to go.
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Rebased. And changed the commit message title to fit into the widely used patter. |
ZijunZhaoCCK
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Sep 19, 2023
The Z#_HI register definitions were created during the very early SVE enablement work and before the SVE calling convention was locked in. As they look entirely unused, they need to go.
|
@pawosm-arm @paulwalker-arm Do you know why there were codegen changes with this commit? |
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This wasn't investigated because with the definitions being unused I figured this was the standard noise you sometimes get when tablegen defs get reordered. I guess it's possible the fake sub registers were blocking a code path or two. |
zahiraam
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Oct 24, 2023
The Z#_HI register definitions were created during the very early SVE enablement work and before the SVE calling convention was locked in. As they look entirely unused, they need to go.
zahiraam
pushed a commit
to tahonermann/llvm-project
that referenced
this pull request
Oct 24, 2023
The Z#_HI register definitions were created during the very early SVE enablement work and before the SVE calling convention was locked in. As they look entirely unused, they need to go.
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The Z#_HI register definitions were created during the very early SVE enablement work and before the SVE calling convention was locked in.
As they look entirely unused, they need to go.