[RISCV] Extend InstSeq (used in constant mat) to support multiple live regs #67159
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…e regs This moves the logic for constant materialization with an additional vreg into common code. It does so by extending the InstSeq construct to support multiple live values in the sequence. This converts an InstSeq from being a linear chain of instructions to being a DAG of instructions. Note that the emergency-slot.mir test change is in principle a bug fix; we're setting kill flags on a register which has later usage. Its probably an uninteresting bug in practice since it only happens on X0 which is a constant physreg and thus the kill flag is fairly meaningless.
topperc
reviewed
Sep 25, 2023
| case RISCVMatInt::RegReg: | ||
| BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg) | ||
| .addReg(SrcReg, RegState::Kill) | ||
| .addReg(SrcReg, RegState::Kill) | ||
| .addReg(SrcReg0, getKillRegState(SrcReg0 != RISCV::X0)) |
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Do you mind if I extract this part of the patch and commit it regardless of the rest?
topperc
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Sep 25, 2023
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Posted mostly for discussion. This turned out to be more invasive and fiddly than I'd expected when I first started. My guess is that we probably won't land this, but I wanted to show what the option looked like.
This moves the logic for constant materialization with an additional vreg into common code. It does so by extending the InstSeq construct to support multiple live values in the sequence. This converts an InstSeq from being a linear chain of instructions to being a DAG of instructions.
Note that the emergency-slot.mir test change is in principle a bug fix; we're setting kill flags on a register which has later usage. Its probably an uninteresting bug in practice since it only happens on X0 which is a constant physreg and thus the kill flag is fairly meaningless.