[TableGen][RISCV][GlobalISel] Select G_ICMP, G_LOAD, G_ZEXTLOAD and G_STORE

[nitinjohnraj]

This PR represents 3 patches:

1. [TableGen] Handle pointer types based on the hardware mode in tablegen
2. [RISCV][GlobalISel] Select G_ICMP
3. [RISCV][GlobalISel] Select G_LOAD, G_ZEXTLOAD, G_STORE

Patches 2 and 3 are dependent on 1. Since we don't have stacked diff workflow on github, we are using one PR with 3 patches which we will manually commit when approved.

[github-actions]

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff 09c544e76012e7559a7be7fca34aeb8584da91a7 3750758854a98da5c05e780a0a41bd1cd54c47c0 -- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp llvm/utils/TableGen/InfoByHwMode.cpp

View the diff from clang-format here.

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 69f2c7ce8874..efd0dfe1bf21 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -109,15 +109,12 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
   return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
 }
 
-
 InstructionSelector::ComplexRendererFns
 RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
   // TODO: Need to get the immediate from a G_PTR_ADD. Should this be done in
   // the combiner?
-  return {{
-        [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
-        [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }
-    }};
+  return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
+           [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }}};
 }
 
 // Tablegen doesn't allow us to write SRLIW/SRAIW/SLLIW patterns because the