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[Clang][RISCV] Support CSRs in clobbered registers of inline assembly #67646

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Oct 23, 2023
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[Clang][RISCV] Support CSRs in clobbered registers of inline assembly #67646

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8 changes: 7 additions & 1 deletion clang/lib/Basic/Targets/RISCV.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ using namespace clang;
using namespace clang::targets;

ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
// clang-format off
static const char *const GCCRegNames[] = {
// Integer registers
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
Expand All @@ -40,7 +41,12 @@ ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",

// CSRs
"fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
};
// clang-format on
return llvm::ArrayRef(GCCRegNames);
}

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44 changes: 44 additions & 0 deletions clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
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@@ -0,0 +1,44 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm %s -o - \
// RUN: | FileCheck %s
// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm %s -o - \
// RUN: | FileCheck %s

// Test RISC-V specific clobbered registers in inline assembly.

// CHECK-LABEL: define {{.*}} void @test_fflags
// CHECK: tail call void asm sideeffect "", "~{fflags}"()
void test_fflags(void) {
asm volatile ("" :::"fflags");
}

// CHECK-LABEL: define {{.*}} void @test_frm
// CHECK: tail call void asm sideeffect "", "~{frm}"()
void test_frm(void) {
asm volatile ("" :::"frm");
}

// CHECK-LABEL: define {{.*}} void @test_vtype
// CHECK: tail call void asm sideeffect "", "~{vtype}"()
void test_vtype(void) {
asm volatile ("" :::"vtype");
}

// CHECK-LABEL: define {{.*}} void @test_vl
// CHECK: tail call void asm sideeffect "", "~{vl}"()
void test_vl(void) {
asm volatile ("" :::"vl");
}

// CHECK-LABEL: define {{.*}} void @test_vxsat
// CHECK: tail call void asm sideeffect "", "~{vxsat}"()
void test_vxsat(void) {
asm volatile ("" :::"vxsat");
}

// CHECK-LABEL: define {{.*}} void @test_vxrm
// CHECK: tail call void asm sideeffect "", "~{vxrm}"()
void test_vxrm(void) {
asm volatile ("" :::"vxrm");
}