[RISCV] Strip W suffix from ADDIW #68425

preames · 2023-10-06T15:43:15Z

The motivation of this change is simply to reduce test duplication. As can be seen in the (massive) test delta, we have many tests whose output differ only due to the use of addi on rv32 vs addiw on rv64 when the high bits are don't care.

As an aside, we don't need to worry about the non-zero immediate restriction on the compressed variants because we're not directly forming the compressed variants. If we happen to get a zero immediate for the ADDI, then either a later optimization will strip the useless instruction or the encoder is responsible for not compressing the instruction.

The original motivation of this change was simply to reduce test duplication. As can be seen in the (massive) test delta, we have many tests whose output differ only due to the use of addi on rv32 vs addiw on rv64 when the high bits are don't care. However, after reading the isa specification, I believe this to also be a compressibility optimization. There doesn't seem to be compressed versions of these instructions (or of slliw despite what the previous comment says), so using the non-W variant should allow the formation of more compressed instructions. As an aside, we don't need to worry about the non-zero immediate restriction on the compressed variants because we're not directly forming the compressed variants. If we happen to get a zero immediate for e.g. the ADDI, then either a later optimization will strip the useless instruction or the encoder is responsible for not compressing the instruction.

llvmbot · 2023-10-06T15:44:26Z

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-risc-v

Changes

The original motivation of this change was simply to reduce test duplication. As can be seen in the (massive) test delta, we have many tests whose output differ only due to the use of addi on rv32 vs addiw on rv64 when the high bits are don't care.

However, after reading the isa specification, I believe this to also be a compressibility optimization. There doesn't seem to be compressed versions of these instructions (or of slliw despite what the previous comment says), so using the non-W variant should allow the formation of more compressed instructions.

As an aside, we don't need to worry about the non-zero immediate restriction on the compressed variants because we're not directly forming the compressed variants. If we happen to get a zero immediate for e.g. the ADDI, then either a later optimization will strip the useless instruction or the encoder is responsible for not compressing the instruction.

Patch is 1.49 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/68425.diff

113 Files Affected:

(modified) llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp (+9-5)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/add-before-shl.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/add-imm.ll (+10-10)
(modified) llvm/test/CodeGen/RISCV/addimm-mulimm.ll (+28-28)
(modified) llvm/test/CodeGen/RISCV/and.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll (+16-16)
(modified) llvm/test/CodeGen/RISCV/atomic-rmw.ll (+91-91)
(modified) llvm/test/CodeGen/RISCV/atomic-signext.ll (+11-11)
(modified) llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/bfloat-convert.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/bfloat.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/bittest.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/bswap-bitreverse.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/calling-conv-half.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll (+12-12)
(modified) llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/div-by-constant.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/div-pow2.ll (+14-14)
(modified) llvm/test/CodeGen/RISCV/div.ll (+10-10)
(modified) llvm/test/CodeGen/RISCV/double-convert.ll (+11-11)
(modified) llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/float-convert.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/half-convert.ll (+23-23)
(modified) llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll (+14-30)
(modified) llvm/test/CodeGen/RISCV/iabs.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/imm.ll (+10-10)
(modified) llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll (+18-18)
(modified) llvm/test/CodeGen/RISCV/machine-outliner-throw.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/memcpy.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/neg-abs.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/overflow-intrinsics.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rem.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/rv64xtheadbb.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rv64zbb.ll (+14-14)
(modified) llvm/test/CodeGen/RISCV/rv64zbkb.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll (+348-707)
(modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll (+881-1774)
(modified) llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll (+75-155)
(modified) llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll (+150-310)
(modified) llvm/test/CodeGen/RISCV/rvv/combine-sats.ll (+17-30)
(modified) llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll (+742-1495)
(modified) llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll (+131-260)
(modified) llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll (+258-527)
(modified) llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll (+542-1107)
(modified) llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll (+648-1271)
(modified) llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll (+687-1399)
(modified) llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll (+667-1338)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll (+21-21)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll (+120-248)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll (+19-37)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll (+2200-3304)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll (+281-534)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll (+376-768)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll (+183-478)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll (+888-1800)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll (+239-450)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll (+52-99)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll (+24-50)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll (+44-94)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll (+72-141)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll (+53-110)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll (+326-661)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll (+62-39)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll (+19-33)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll (+31-58)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll (+10-21)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll (+40-79)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll (+18-18)
(modified) llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll (+277-537)
(modified) llvm/test/CodeGen/RISCV/rvv/pr61561.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/rvv/select-sra.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll (+61-119)
(modified) llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll (+22-22)
(modified) llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll (+65-131)
(modified) llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll (+99-210)
(modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll (+59-56)
(modified) llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll (+77-155)
(modified) llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll (+110-231)
(modified) llvm/test/CodeGen/RISCV/select-binop-identity.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/select-constant-xor.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/select-to-and-zext.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/select.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll (+6-13)
(modified) llvm/test/CodeGen/RISCV/sextw-removal.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/shl-demanded.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/shlimm-addimm.ll (+10-10)
(modified) llvm/test/CodeGen/RISCV/signed-truncation-check.ll (+18-18)
(modified) llvm/test/CodeGen/RISCV/srem-lkk.ll (+13-13)
(modified) llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/srem-vector-lkk.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/urem-lkk.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll (+13-13)
(modified) llvm/test/CodeGen/RISCV/urem-vector-lkk.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/vararg.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/xaluo.ll (+3-3)

diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 439a1bb6e1e69d2..3a756db977904b6 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -12,11 +12,12 @@
 // extended bits aren't consumed or because the input was already sign extended
 // by an earlier instruction.
 //
-// Then it removes the -w suffix from addw, slliw and mulw instructions
-// whenever all users are dependent only on the lower word of the result of the
-// instruction. We do this only for addw, slliw, and mulw because the -w forms
-// are less compressible: c.add and c.slli have a larger register encoding than
-// their w counterparts, and there's no compressible version of mulw.
+// Then it removes the -w suffix from opw instructions whenever all users are
+// dependent only on the lower word of the result of the instruction.  This is
+// profitable for addw because c.add has a larger register encoding than c.addw.
+// For the remaining opw instructions, there is no compressed w variant. This
+// tramsform also has the side effect of making RV32 and RV64 codegen for 32
+// bit constants match which helps reduce check duplication in LIT tests.
 //
 //===---------------------------------------------------------------------===//
 
@@ -661,8 +662,11 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
       default:
         continue;
       case RISCV::ADDW:  Opc = RISCV::ADD;  break;
+      case RISCV::ADDIW: Opc = RISCV::ADDI; break;
       case RISCV::MULW:  Opc = RISCV::MUL;  break;
       case RISCV::SLLIW: Opc = RISCV::SLLI; break;
+      case RISCV::SRLIW: Opc = RISCV::SRLI; break;
+      case RISCV::SRAIW: Opc = RISCV::SRAI; break;
       }
 
       if (hasAllWUsers(MI, ST, MRI)) {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
index c503d6541b0a577..16a81b79b2f3fc2 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
@@ -34,9 +34,9 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) {
 ; RV64IM-LABEL: add_i8_signext_i32:
 ; RV64IM:       # %bb.0: # %entry
 ; RV64IM-NEXT:    slli a0, a0, 24
-; RV64IM-NEXT:    sraiw a0, a0, 24
+; RV64IM-NEXT:    srai a0, a0, 24
 ; RV64IM-NEXT:    slli a1, a1, 24
-; RV64IM-NEXT:    sraiw a1, a1, 24
+; RV64IM-NEXT:    srai a1, a1, 24
 ; RV64IM-NEXT:    addw a0, a0, a1
 ; RV64IM-NEXT:    ret
 entry:
diff --git a/llvm/test/CodeGen/RISCV/add-before-shl.ll b/llvm/test/CodeGen/RISCV/add-before-shl.ll
index a41664fde38581c..274f1cef49aa955 100644
--- a/llvm/test/CodeGen/RISCV/add-before-shl.ll
+++ b/llvm/test/CodeGen/RISCV/add-before-shl.ll
@@ -25,7 +25,7 @@ define signext i32 @add_small_const(i32 signext %a) nounwind {
 ;
 ; RV64I-LABEL: add_small_const:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, 1
+; RV64I-NEXT:    addi a0, a0, 1
 ; RV64I-NEXT:    slli a0, a0, 56
 ; RV64I-NEXT:    srai a0, a0, 56
 ; RV64I-NEXT:    jalr zero, 0(ra)
@@ -39,7 +39,7 @@ define signext i32 @add_small_const(i32 signext %a) nounwind {
 ;
 ; RV64C-LABEL: add_small_const:
 ; RV64C:       # %bb.0:
-; RV64C-NEXT:    c.addiw a0, 1
+; RV64C-NEXT:    c.addi a0, 1
 ; RV64C-NEXT:    c.slli a0, 56
 ; RV64C-NEXT:    c.srai a0, 56
 ; RV64C-NEXT:    c.jr ra
@@ -78,7 +78,7 @@ define signext i32 @add_large_const(i32 signext %a) nounwind {
 ; RV64C-LABEL: add_large_const:
 ; RV64C:       # %bb.0:
 ; RV64C-NEXT:    c.lui a1, 1
-; RV64C-NEXT:    c.addiw a1, -1
+; RV64C-NEXT:    c.addi a1, -1
 ; RV64C-NEXT:    c.add a0, a1
 ; RV64C-NEXT:    c.slli a0, 48
 ; RV64C-NEXT:    c.srai a0, 48
@@ -118,7 +118,7 @@ define signext i32 @add_huge_const(i32 signext %a) nounwind {
 ; RV64C-LABEL: add_huge_const:
 ; RV64C:       # %bb.0:
 ; RV64C-NEXT:    c.lui a1, 8
-; RV64C-NEXT:    c.addiw a1, -1
+; RV64C-NEXT:    c.addi a1, -1
 ; RV64C-NEXT:    c.add a0, a1
 ; RV64C-NEXT:    c.slli a0, 48
 ; RV64C-NEXT:    c.srai a0, 48
@@ -139,7 +139,7 @@ define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
 ;
 ; RV64I-LABEL: add_non_machine_type:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, 256
+; RV64I-NEXT:    addi a0, a0, 256
 ; RV64I-NEXT:    slli a0, a0, 52
 ; RV64I-NEXT:    srai a0, a0, 40
 ; RV64I-NEXT:    jalr zero, 0(ra)
@@ -153,7 +153,7 @@ define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
 ;
 ; RV64C-LABEL: add_non_machine_type:
 ; RV64C:       # %bb.0:
-; RV64C-NEXT:    addiw a0, a0, 256
+; RV64C-NEXT:    addi a0, a0, 256
 ; RV64C-NEXT:    c.slli a0, 52
 ; RV64C-NEXT:    c.srai a0, 40
 ; RV64C-NEXT:    c.jr ra
diff --git a/llvm/test/CodeGen/RISCV/add-imm.ll b/llvm/test/CodeGen/RISCV/add-imm.ll
index 700fec0192d3e74..52751f1c224211f 100644
--- a/llvm/test/CodeGen/RISCV/add-imm.ll
+++ b/llvm/test/CodeGen/RISCV/add-imm.ll
@@ -29,7 +29,7 @@ define i32 @add_positive_low_bound_accept(i32 %a) nounwind {
 ;
 ; RV64I-LABEL: add_positive_low_bound_accept:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, 2047
+; RV64I-NEXT:    addi a0, a0, 2047
 ; RV64I-NEXT:    addiw a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 2048
@@ -45,7 +45,7 @@ define i32 @add_positive_high_bound_accept(i32 %a) nounwind {
 ;
 ; RV64I-LABEL: add_positive_high_bound_accept:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, 2047
+; RV64I-NEXT:    addi a0, a0, 2047
 ; RV64I-NEXT:    addiw a0, a0, 2047
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 4094
@@ -63,7 +63,7 @@ define i32 @add_positive_high_bound_reject(i32 %a) nounwind {
 ; RV64I-LABEL: add_positive_high_bound_reject:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -1
+; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    addw a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 4095
@@ -93,7 +93,7 @@ define i32 @add_negative_high_bound_accept(i32 %a) nounwind {
 ;
 ; RV64I-LABEL: add_negative_high_bound_accept:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, -2048
+; RV64I-NEXT:    addi a0, a0, -2048
 ; RV64I-NEXT:    addiw a0, a0, -1
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, -2049
@@ -109,7 +109,7 @@ define i32 @add_negative_low_bound_accept(i32 %a) nounwind {
 ;
 ; RV64I-LABEL: add_negative_low_bound_accept:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, -2048
+; RV64I-NEXT:    addi a0, a0, -2048
 ; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, -4096
@@ -127,7 +127,7 @@ define i32 @add_negative_low_bound_reject(i32 %a) nounwind {
 ; RV64I-LABEL: add_negative_low_bound_reject:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1048575
-; RV64I-NEXT:    addiw a1, a1, -1
+; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    addw a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, -4097
@@ -143,7 +143,7 @@ define i32 @add32_accept(i32 %a) nounwind {
 ;
 ; RV64I-LABEL: add32_accept:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, 2047
+; RV64I-NEXT:    addi a0, a0, 2047
 ; RV64I-NEXT:    addiw a0, a0, 952
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 2999
@@ -159,7 +159,7 @@ define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
 ;
 ; RV64I-LABEL: add32_sext_accept:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, 2047
+; RV64I-NEXT:    addi a0, a0, 2047
 ; RV64I-NEXT:    addiw a0, a0, 952
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 2999
@@ -178,7 +178,7 @@ define signext i32 @add32_sext_reject_on_rv64(i32 signext %a) nounwind {
 ;
 ; RV64I-LABEL: add32_sext_reject_on_rv64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addiw a0, a0, 2047
+; RV64I-NEXT:    addi a0, a0, 2047
 ; RV64I-NEXT:    addiw a0, a0, 953
 ; RV64I-NEXT:    lui a1, %hi(gv0)
 ; RV64I-NEXT:    sw a0, %lo(gv0)(a1)
@@ -231,7 +231,7 @@ define void @add32_reject() nounwind {
 ; RV64I-NEXT:    lui a2, %hi(gb)
 ; RV64I-NEXT:    lw a3, %lo(gb)(a2)
 ; RV64I-NEXT:    lui a4, 1
-; RV64I-NEXT:    addiw a4, a4, -1096
+; RV64I-NEXT:    addi a4, a4, -1096
 ; RV64I-NEXT:    add a1, a1, a4
 ; RV64I-NEXT:    add a3, a3, a4
 ; RV64I-NEXT:    sw a1, %lo(ga)(a0)
diff --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
index d1bc480455dd35f..48fa69e10456563 100644
--- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
+++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
@@ -84,7 +84,7 @@ define i32 @add_mul_combine_accept_b1(i32 %x) {
 ; RV64IMB-NEXT:    li a1, 23
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 50
-; RV64IMB-NEXT:    addiw a1, a1, 1119
+; RV64IMB-NEXT:    addi a1, a1, 1119
 ; RV64IMB-NEXT:    addw a0, a0, a1
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 8953
@@ -107,7 +107,7 @@ define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
 ; RV64IMB-NEXT:    li a1, 23
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 50
-; RV64IMB-NEXT:    addiw a1, a1, 1119
+; RV64IMB-NEXT:    addi a1, a1, 1119
 ; RV64IMB-NEXT:    addw a0, a0, a1
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 8953
@@ -153,7 +153,7 @@ define i32 @add_mul_combine_reject_a1(i32 %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_a1:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 1971
+; RV64IMB-NEXT:    addi a0, a0, 1971
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    ret
@@ -172,7 +172,7 @@ define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_a2:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 1971
+; RV64IMB-NEXT:    addi a0, a0, 1971
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    ret
@@ -217,7 +217,7 @@ define i32 @add_mul_combine_reject_c1(i32 %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_c1:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 1000
+; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    sext.w a0, a0
@@ -237,7 +237,7 @@ define signext i32 @add_mul_combine_reject_c2(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_c2:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 1000
+; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    sext.w a0, a0
@@ -349,7 +349,7 @@ define i32 @add_mul_combine_reject_e1(i32 %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_e1:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 1971
+; RV64IMB-NEXT:    addi a0, a0, 1971
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    ret
@@ -368,7 +368,7 @@ define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_e2:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 1971
+; RV64IMB-NEXT:    addi a0, a0, 1971
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    ret
@@ -414,7 +414,7 @@ define i32 @add_mul_combine_reject_f1(i32 %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_f1:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 1972
+; RV64IMB-NEXT:    addi a0, a0, 1972
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 11
@@ -435,7 +435,7 @@ define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_f2:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 1972
+; RV64IMB-NEXT:    addi a0, a0, 1972
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 11
@@ -483,7 +483,7 @@ define i32 @add_mul_combine_reject_g1(i32 %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_g1:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 100
+; RV64IMB-NEXT:    addi a0, a0, 100
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    addiw a0, a0, 10
@@ -504,7 +504,7 @@ define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_g2:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 100
+; RV64IMB-NEXT:    addi a0, a0, 100
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    addiw a0, a0, 10
@@ -581,9 +581,9 @@ define i32 @mul3000_add8990_a(i32 %x) {
 ;
 ; RV64IMB-LABEL: mul3000_add8990_a:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 3
+; RV64IMB-NEXT:    addi a0, a0, 3
 ; RV64IMB-NEXT:    lui a1, 1
-; RV64IMB-NEXT:    addiw a1, a1, -1096
+; RV64IMB-NEXT:    addi a1, a1, -1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, -10
 ; RV64IMB-NEXT:    ret
@@ -604,9 +604,9 @@ define signext i32 @mul3000_add8990_b(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: mul3000_add8990_b:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 3
+; RV64IMB-NEXT:    addi a0, a0, 3
 ; RV64IMB-NEXT:    lui a1, 1
-; RV64IMB-NEXT:    addiw a1, a1, -1096
+; RV64IMB-NEXT:    addi a1, a1, -1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, -10
 ; RV64IMB-NEXT:    ret
@@ -656,9 +656,9 @@ define i32 @mul3000_sub8990_a(i32 %x) {
 ;
 ; RV64IMB-LABEL: mul3000_sub8990_a:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, -3
+; RV64IMB-NEXT:    addi a0, a0, -3
 ; RV64IMB-NEXT:    lui a1, 1
-; RV64IMB-NEXT:    addiw a1, a1, -1096
+; RV64IMB-NEXT:    addi a1, a1, -1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 10
 ; RV64IMB-NEXT:    ret
@@ -679,9 +679,9 @@ define signext i32 @mul3000_sub8990_b(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: mul3000_sub8990_b:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, -3
+; RV64IMB-NEXT:    addi a0, a0, -3
 ; RV64IMB-NEXT:    lui a1, 1
-; RV64IMB-NEXT:    addiw a1, a1, -1096
+; RV64IMB-NEXT:    addi a1, a1, -1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 10
 ; RV64IMB-NEXT:    ret
@@ -732,9 +732,9 @@ define i32 @mulneg3000_add8990_a(i32 %x) {
 ;
 ; RV64IMB-LABEL: mulneg3000_add8990_a:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, -3
+; RV64IMB-NEXT:    addi a0, a0, -3
 ; RV64IMB-NEXT:    lui a1, 1048575
-; RV64IMB-NEXT:    addiw a1, a1, 1096
+; RV64IMB-NEXT:    addi a1, a1, 1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, -10
 ; RV64IMB-NEXT:    ret
@@ -755,9 +755,9 @@ define signext i32 @mulneg3000_add8990_b(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: mulneg3000_add8990_b:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, -3
+; RV64IMB-NEXT:    addi a0, a0, -3
 ; RV64IMB-NEXT:    lui a1, 1048575
-; RV64IMB-NEXT:    addiw a1, a1, 1096
+; RV64IMB-NEXT:    addi a1, a1, 1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, -10
 ; RV64IMB-NEXT:    ret
@@ -808,9 +808,9 @@ define i32 @mulneg3000_sub8990_a(i32 %x) {
 ;
 ; RV64IMB-LABEL: mulneg3000_sub8990_a:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 3
+; RV64IMB-NEXT:    addi a0, a0, 3
 ; RV64IMB-NEXT:    lui a1, 1048575
-; RV64IMB-NEXT:    addiw a1, a1, 1096
+; RV64IMB-NEXT:    addi a1, a1, 1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 10
 ; RV64IMB-NEXT:    ret
@@ -831,9 +831,9 @@ define signext i32 @mulneg3000_sub8990_b(i32 signext %x) {
 ;
 ; RV64IMB-LABEL: mulneg3000_sub8990_b:
 ; RV64IMB:       # %bb.0:
-; RV64IMB-NEXT:    addiw a0, a0, 3
+; RV64IMB-NEXT:    addi a0, a0, 3
 ; RV64IMB-NEXT:    lui a1, 1048575
-; RV64IMB-NEXT:    addiw a1, a1, 1096
+; RV64IMB-NEXT:    addi a1, a1, 1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 10
 ; RV64IMB-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/and.ll b/llvm/test/CodeGen/RISCV/and.ll
index 5eff422013da6a8..79e3b954c50d8d8 100644
--- a/llvm/test/CodeGen/RISCV/and.ll
+++ b/llvm/test/CodeGen/RISCV/and.ll
@@ -195,7 +195,7 @@ define i64 @and64_0x7fffffff00000000(i64 %x) {
 ; RV64I-LABEL: and64_0x7fffffff00000000:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 524288
-; RV64I-NEXT:    addiw a1, a1, -1
+; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index f900b5161f75128..eea4cb72938af23 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -1104,7 +1104,7 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounw
 ; RV64IA-NEXT:    andi a3, a0, -4
 ; RV64IA-NEXT:    slli a0, a0, 3
 ; RV64IA-NEXT:    lui a4, 16
-; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    addi a4, a4, -1
 ; RV64IA-NEXT:    sllw a5, a4, a0
 ; RV64IA-NEXT:    and a1, a1, a4
 ; RV64IA-NEXT:    sllw a1, a1, a0
@@ -1206,7 +1206,7 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
 ; RV64IA-WMO-NEXT:    andi a3, a0, -4
 ; RV64IA-WMO-NEXT:    slli a0, a0, 3
 ; RV64IA-WMO-NEXT:    lui a4, 16
-; RV64IA-WMO-NEXT:    addiw a4, a4, -1
+; RV64IA-WMO-NEXT:    addi a4, a4, -1
 ; RV64IA-WMO-NEXT:    sllw a5, a4, a0
 ; RV64IA-WMO-NEXT:    and a1, a1, a4
 ; RV64IA-WMO-NEXT:    sllw a1, a1, a0
@@ -1230,7 +1230,7 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
 ; RV64IA-TSO-NEXT:    andi a3, a0, -4
 ; RV64IA-TSO-NEXT:    slli a0, a0, 3
 ; RV64IA-TSO-NEXT:    lui a4, 16
-; RV64IA-TSO-NEXT:    addiw a4, a4, -1
+; RV64IA-TSO-NEXT:    addi a4, a4, -1
 ; RV64IA-TSO-NEXT:    sllw a5, a4, a0
 ; RV64IA-TSO-NEXT:    and a1, a1, a4
 ; RV64IA-TSO-NEXT:    sllw a1, a1, a0
@@ -1332,7 +1332,7 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
 ; RV64IA-WMO-NEXT:    andi a3, a0, -4
 ; RV64IA-WMO-NEXT:    slli a0, a0, 3
 ; RV64IA-WMO-NEXT:    lui a4, 16
-; RV64IA-WMO-NEXT:    addiw a4, a4, -1
+; RV64IA-WMO-NEXT:    addi a4, a4, -1
 ; RV64IA-WMO-NEXT:    sllw a5, a4, a0
 ; RV64IA-WMO-NEXT:    and a1, a1, a4
 ; RV64IA-WMO-NEXT:    sllw a1, a1, a0
@@ -1356,7 +1356,7 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
 ; RV64IA-TSO-NEXT:    andi a3, a0, -4
 ; RV64IA-TSO-NEXT:    slli a0, a0, 3
 ; RV64IA-TSO-NEXT:    lui a4, 16
-; RV64IA-TSO-NEXT:    addiw a4, a4, -1
+; RV64IA-TSO-NEXT:    addi a4, a4, -1
 ; RV64IA-TSO-NEXT:    sllw a5, a4, a0
 ; RV64IA-TSO-NEXT:    and a1, a1, a4
 ; RV64IA-TSO-NEXT:    sllw a1, a1, a0
@@ -1458,7 +1458,7 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
 ; RV64IA-WMO-NEXT:    andi a3, a0, -4
 ; RV64IA-WMO-NEXT:    slli a0, a0, 3
 ; RV64IA-WMO-NEXT:    lui a4, 16
-; RV64IA-WMO-NEXT:    addiw a4, a4, -1
+; RV64IA-WMO-NEXT:    addi a4, a4, -1
 ; RV64IA-WMO-NEXT:    sllw a5, a4, a0
 ; RV64IA-WMO-NEXT:    and a1, a1, a4
 ; RV64IA-WMO-NEXT:    sllw a1, a1, a0
@@ -1482,7 +1482,7 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
 ; RV64IA-TSO-NEXT:    andi a3, a0, -4
 ; RV64IA-TSO-NEXT:    slli a0, a0, 3
 ; RV64IA-TSO-NEXT:    lui a4, 16
-; RV64IA-TSO-NEXT:    addiw a4, a4, -1
+; RV64IA-TSO-NEXT:    addi a4, a4, -1
 ; RV64IA-TSO-NEXT:    sllw a5, a4, a0
 ; RV64IA-TSO-NEXT:    and a1, a1, a4
 ; RV64IA-TSO-NEXT:    sllw a1, a1, a0
@@ -1584,7 +1584,7 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
 ; RV64IA-WMO-NEXT:    andi a3, a0, -4
 ; RV64IA-WMO-NEXT:    slli a0, a0, 3
 ; RV64IA-WMO-NEXT:    lui a4, 16
-; RV64IA-WMO-NEXT:    addiw a4, a4, -1
+; RV64IA-WMO-NEXT:    addi a4, a4, -1
 ; RV64IA-WMO-NEXT:    sllw a5, a4, a0
 ; RV64IA-WMO-NEXT:    and a1, a1, a4
 ; RV64IA-WMO-NEXT:    sllw a1, a1, a0
@@ -1608,7 +1608,7 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
 ; RV64IA-TSO-NEXT:    andi a3, a0, -4
 ; RV64IA-TSO-NEXT:    slli a0, a0, 3
 ; RV64IA-TSO-NEXT:    lui a4, 16
-; RV64IA-TSO-NEXT:    addiw a4, a4, -1
+; RV64IA-TSO-NEXT:    addi a4, a4, -1
 ; RV64IA-TSO-NEXT:    sllw a5, a4, a0
 ; RV64IA-TSO-NEXT:    and a1, a1, a4
 ; RV64IA-TSO-NEXT:    sllw a1, a1, a0
@@ -1710,7 +1710,7 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
 ; RV64IA-WMO-NEXT:    andi a3, a0, -4
 ; RV64IA-WMO-NEXT:    slli a0, a0, 3
 ; RV64IA-WMO-NEXT:    lui a4, 16
-; RV64IA-WMO-NEXT:    addiw a4, a4, -1
+; RV64IA-WMO-NEXT:    addi a4, a4, -1
 ; RV64IA-WMO-NEXT:    sllw a5, a4, a0
 ; RV64IA-WMO-NEXT:    and a1, a1, a4
 ; RV64IA-WMO-NEXT:    sllw a1, a1, a0
@@ -1734,7 +1734,7 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, ...
[truncated]

github-actions · 2023-10-06T15:44:47Z

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff ffdae1a11786b482104371defffe2e5772fbf0b1 fd4f5cdce9683a10508159afc234e85f8b459baf -- llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

View the diff from clang-format here.

diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index a33ad8a194af..85b899503b81 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -664,7 +664,9 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
       default:
         continue;
       case RISCV::ADDW:  Opc = RISCV::ADD;  break;
-      case RISCV::ADDIW: Opc = RISCV::ADDI; break;
+      case RISCV::ADDIW:
+        Opc = RISCV::ADDI;
+        break;
       case RISCV::MULW:  Opc = RISCV::MUL;  break;
       case RISCV::SLLIW: Opc = RISCV::SLLI; break;
       }

topperc · 2023-10-06T15:57:43Z

I don't think it's safe to do this for SRAIW and SRLIW. SRAIW copies bit 31 to all the shifted right bits, SRAI copies bit 63. SRLIW inserts zeros starting at bit 31, SRLI starts at bit 63.

topperc · 2023-10-06T16:07:07Z

llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

+// Then it removes the -w suffix from opw instructions whenever all users are
+// dependent only on the lower word of the result of the instruction.  This is
+// profitable for addw because c.add has a larger register encoding than c.addw.
+// For the remaining opw instructions, there is no compressed w variant. This


There is a c.addiw.

C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into addiw rd, rd, imm. The immediate can be zero for C.ADDIW, where this corresponds to sext.w rd. C.ADDIW is only valid when rd̸=x0; the code points with rd=x0 are reserved.

Agreed, need to fix comment.

topperc · 2023-10-06T16:09:43Z

llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

-// whenever all users are dependent only on the lower word of the result of the
-// instruction. We do this only for addw, slliw, and mulw because the -w forms
-// are less compressible: c.add and c.slli have a larger register encoding than
-// their w counterparts, and there's no compressible version of mulw.


This comment was incorrect. c.mul was added with Zcb.

preames · 2023-10-06T16:33:29Z

I don't think it's safe to do this for SRAIW and SRLIW. SRAIW copies bit 31 to all the shifted right bits, SRAI copies bit 63. SRLIW inserts zeros starting at bit 31, SRLI starts at bit 63.

Are you sure about this semantic? The wording from the specification simple says "SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] ̸= 0 are reserved." I wouldn't get your stated semantic from this without some very tortured reading of "operated on 32-bit values".

Assuming you're correct about the semantic, I definitely agree these are unsound and need removed.

topperc · 2023-10-06T16:40:01Z

I don't think it's safe to do this for SRAIW and SRLIW. SRAIW copies bit 31 to all the shifted right bits, SRAI copies bit 63. SRLIW inserts zeros starting at bit 31, SRLI starts at bit 63.

Are you sure about this semantic? The wording from the specification simple says "SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] ̸= 0 are reserved." I wouldn't get your stated semantic from this without some very tortured reading of "operated on 32-bit values".

Assuming you're correct about the semantic, I definitely agree these are unsound and need removed.

I'm pretty sure. These are our isel patterns for them. Which are we get from type legalization of i32 lshr/ashr.

def : Pat<(i64 (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
(SRAIW GPR:$rs1, uimm5:$shamt)>;

preames · 2023-10-06T16:51:07Z

(Changes planned)

topperc

LGTM

llvmbot added backend:RISC-V llvm:globalisel labels Oct 6, 2023

topperc reviewed Oct 6, 2023

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preames added 2 commits October 6, 2023 09:53

Back out unsound shift changes

3ac5a4c

Rework comment to clarify/correct

fd4f5cd

preames changed the title ~~[RISCV] Strip W suffix from ADDIW, SRLIW, and SRAIW~~ [RISCV] Strip W suffix from ADDIW Oct 6, 2023

topperc approved these changes Oct 6, 2023

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preames merged commit 8624075 into llvm:main Oct 6, 2023
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preames deleted the pr-riscv-optw-addiw branch October 6, 2023 17:28

stepthomas mentioned this pull request Oct 10, 2023

AMDGPU stepthomas atomic csub no rtn forms ver2 stepthomas/llvm-project#1

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[RISCV] Strip W suffix from ADDIW #68425

[RISCV] Strip W suffix from ADDIW #68425

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[RISCV] Strip W suffix from ADDIW #68425

[RISCV] Strip W suffix from ADDIW #68425

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