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[RISCV][GISel] Add regbank selection for G_FADD/G_FSUB/G_FMUL/G_FDIV with F/D extensions. #69805

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merged 1 commit into from
Oct 25, 2023
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[RISCV][GISel] Add regbank selection for G_FADD/G_FSUB/G_FMUL/G_FDIV with F/D extensions. #69805

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35 changes: 31 additions & 4 deletions llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26,12 +26,16 @@ namespace RISCV {

RegisterBankInfo::PartialMapping PartMappings[] = {
{0, 32, GPRRegBank},
{0, 64, GPRRegBank}
{0, 64, GPRRegBank},
{0, 32, FPRRegBank},
{0, 64, FPRRegBank},
};

enum PartialMappingIdx {
PMI_GPR32 = 0,
PMI_GPR64 = 1
PMI_GPR64 = 1,
PMI_FPR32 = 2,
PMI_FPR64 = 3,
};

RegisterBankInfo::ValueMapping ValueMappings[] = {
Expand All @@ -44,13 +48,23 @@ RegisterBankInfo::ValueMapping ValueMappings[] = {
// Maximum 3 GPR operands; 64 bit.
{&PartMappings[PMI_GPR64], 1},
{&PartMappings[PMI_GPR64], 1},
{&PartMappings[PMI_GPR64], 1}
{&PartMappings[PMI_GPR64], 1},
// Maximum 3 FPR operands; 32 bit.
{&PartMappings[PMI_FPR32], 1},
{&PartMappings[PMI_FPR32], 1},
{&PartMappings[PMI_FPR32], 1},
// Maximum 3 FPR operands; 64 bit.
{&PartMappings[PMI_FPR64], 1},
{&PartMappings[PMI_FPR64], 1},
{&PartMappings[PMI_FPR64], 1},
};

enum ValueMappingsIdx {
InvalidIdx = 0,
GPR32Idx = 1,
GPR64Idx = 4
GPR64Idx = 4,
FPR32Idx = 7,
FPR64Idx = 10,
};
} // namespace RISCV
} // namespace llvm
Expand Down Expand Up @@ -101,6 +115,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
return Mapping;
}

const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();

unsigned GPRSize = getMaximumSize(RISCV::GPRRegBankID);
assert((GPRSize == 32 || GPRSize == 64) && "Unexpected GPR size");

Expand Down Expand Up @@ -158,6 +175,16 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OperandsMapping = getOperandsMapping(
{GPRValueMapping, GPRValueMapping, GPRValueMapping, GPRValueMapping});
break;
case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB:
case TargetOpcode::G_FMUL:
case TargetOpcode::G_FDIV: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
OperandsMapping = Ty.getSizeInBits() == 64
? &RISCV::ValueMappings[RISCV::FPR64Idx]
: &RISCV::ValueMappings[RISCV::FPR32Idx];
break;
}
default:
return getInvalidInstructionMapping();
}
Expand Down
192 changes: 192 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,192 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s

---
name: fadd_f32
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fadd_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
; CHECK-NEXT: $f10_f = COPY [[FADD]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:_(s32) = COPY $f10_f
%1:_(s32) = COPY $f11_f
%2:_(s32) = G_FADD %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fsub_f32
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fsub_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]]
; CHECK-NEXT: $f10_f = COPY [[FSUB]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:_(s32) = COPY $f10_f
%1:_(s32) = COPY $f11_f
%2:_(s32) = G_FSUB %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fmul_f32
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fmul_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s32) = G_FMUL [[COPY]], [[COPY1]]
; CHECK-NEXT: $f10_f = COPY [[FMUL]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:_(s32) = COPY $f10_f
%1:_(s32) = COPY $f11_f
%2:_(s32) = G_FMUL %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fdiv_f32
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_f, $f11_f

; CHECK-LABEL: name: fdiv_f32
; CHECK: liveins: $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]]
; CHECK-NEXT: $f10_f = COPY [[FDIV]](s32)
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:_(s32) = COPY $f10_f
%1:_(s32) = COPY $f11_f
%2:_(s32) = G_FDIV %0, %1
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: fadd_f64
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fadd_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]]
; CHECK-NEXT: $f10_d = COPY [[FADD]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:_(s64) = COPY $f10_d
%1:_(s64) = COPY $f11_d
%2:_(s64) = G_FADD %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
---
name: fsub_f64
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fsub_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]]
; CHECK-NEXT: $f10_d = COPY [[FSUB]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:_(s64) = COPY $f10_d
%1:_(s64) = COPY $f11_d
%2:_(s64) = G_FSUB %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
---
name: fmul_f64
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fmul_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s64) = G_FMUL [[COPY]], [[COPY1]]
; CHECK-NEXT: $f10_d = COPY [[FMUL]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:_(s64) = COPY $f10_d
%1:_(s64) = COPY $f11_d
%2:_(s64) = G_FMUL %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
---
name: fdiv_f64
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $f10_d, $f11_d

; CHECK-LABEL: name: fdiv_f64
; CHECK: liveins: $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]]
; CHECK-NEXT: $f10_d = COPY [[FDIV]](s64)
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:_(s64) = COPY $f10_d
%1:_(s64) = COPY $f11_d
%2:_(s64) = G_FDIV %0, %1
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...