[AMDGPU] Set SchedRW = Write64Bit on V_MOV_B64

[rampitec]

This is mostly NFCI as V_MOV_B64_PSEUDO is selected instead and expanded past RA.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

Changes

This is mostly NFCI as V_MOV_B64_PSEUDO is selected instead and expanded past RA.

---

Full diff: https://github.com/llvm/llvm-project/pull/70135.diff

1 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/VOP1Instructions.td (+1-1)

diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 734db326fb77ddd..9c19091e3d583f1 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -221,7 +221,7 @@ def VOPProfile_MOV : VOPProfile <[i32, i32, untyped, untyped]> {
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 defm V_MOV_B32 : VOP1Inst <"v_mov_b32", VOPProfile_MOV, null_frag, 0x8>;
 
-let SubtargetPredicate = isGFX940Plus in
+let SubtargetPredicate = isGFX940Plus, SchedRW = [Write64Bit] in
 defm V_MOV_B64 : VOP1Inst <"v_mov_b64", VOP_I64_I64>;
 } // End isMoveImm = 1
 

[jayfoad]

Makes sense to me.