[RISCV] Add processor definition for XiangShan-NanHu #70294

dtcxzyw · 2023-10-26T05:58:44Z

This PR adds the processor definition for XiangShan-NanHu, an open-source high-performance RISC-V processor.

According to the official documentation, NanHu core supports RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval. I found that NanHu also supports zicbom and zicboz. You can find them in the source code. Features supported by NanHu have been confirmed by @poemonsense.

See also #70232.

Full diff: https://github.com/llvm/llvm-project/pull/70294.diff

3 Files Affected:

(modified) clang/test/Driver/riscv-cpus.c (+14)
(modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2)
(modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+21)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3eaceedce685fc6..70f0a63336bd478 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -20,6 +20,17 @@
 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbkx" "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd" "-target-feature" "+zkne" "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
+// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -62,6 +73,9 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s
 // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
+// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+
 // Check mtune alias CPU has resolved to the right CPU according XLEN.
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
 // MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index b2a04ebdbce628f..8e91eb4c62dd259 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e4008d145ffa572..427e15bea2f8dce 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -243,3 +243,24 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
                                              FeatureStdExtZicbop,
                                              FeatureStdExtZicboz,
                                              FeatureVendorXVentanaCondOps]>;
+
+def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
+                                          NoSchedModel,
+                                          [Feature64Bit,
+                                           FeatureStdExtZicsr,
+                                           FeatureStdExtZifencei,
+                                           FeatureStdExtM,
+                                           FeatureStdExtA,
+                                           FeatureStdExtF,
+                                           FeatureStdExtD,
+                                           FeatureStdExtC,
+                                           FeatureStdExtZba,
+                                           FeatureStdExtZbb,
+                                           FeatureStdExtZbc,
+                                           FeatureStdExtZbs,
+                                           FeatureStdExtZkn,
+                                           FeatureStdExtZksed,
+                                           FeatureStdExtZksh,
+                                           FeatureStdExtSvinval,
+                                           FeatureStdExtZicbom,
+                                           FeatureStdExtZicboz]>;

wangpc-pp · 2023-10-26T07:42:45Z

LGTM in general, except one question: will zicbom and zicboz be in the final RTL?

dtcxzyw · 2023-10-26T09:05:25Z

LGTM in general, except one question: will zicbom and zicboz be in the final RTL?

You can find the full implementation of zicbom and zicboz here: OpenXiangShan/XiangShan@ca18a0b.
cc @poemonsense

wangpc-pp

LGTM

wangpc-pp · 2023-10-26T09:35:49Z

clang/test/Driver/riscv-cpus.c

@@ -20,6 +20,17 @@
 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"

+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s


I prefer to one CHECK line for one feature, but it's OK since other processors aren't in this form.

Sometimes checking that there is no unrelated feature is important. linux-cross.cpp // DEBIAN_I686_M64-SAME: {{^}} provides an example. But here it may not be important.

wangpc-pp · 2023-10-26T09:37:54Z

LGTM in general, except one question: will zicbom and zicboz be in the final RTL?

You can find the full implementation of zicbom and zicboz here: OpenXiangShan/XiangShan@ca18a0b. cc @poemonsense

Please update the official document then. :-)

asb · 2023-10-26T14:51:56Z

@dtcxzyw Could you please confirm the status of this core - is it commercially available, an academic test chip, something else?

poemonsense · 2023-10-26T15:06:18Z

LGTM in general, except one question: will zicbom and zicboz be in the final RTL?

Yes, it's in the final RTL.

poemonsense · 2023-10-26T15:13:15Z

@dtcxzyw Could you please confirm the status of this core - is it commercially available, an academic test chip, something else?

It's maintained by Beijing Institute of Open Source Chip (BOSC), a non-profit organziation founded by companies and researech institutions. It is provided as an open-source CPU Core IP to the third party. It's not an academic testchip.

It's not commercially available now, but there have already been a couple of companies using it as the CPU Core IP. I cannot disclose the progress of commercial chips now but hopefully we will see it soon. There are also some companies using it on FPGAs now.

poemonsense · 2023-10-26T15:18:00Z

Please update the official document then. :-)

I'll do it. We did not list it previously because it is not the usual thing for user programs, as we were initially implementing it for internal usage. Sorry for causing the confusion.

dtcxzyw · 2023-10-26T16:58:10Z

Any more questions about XiangShan? If there is no question, I will merge this PR tomorrow.

MaskRay · 2023-10-27T02:25:20Z

clang/test/Driver/riscv-cpus.c

@@ -20,6 +20,17 @@
 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"

+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s


Sometimes checking that there is no unrelated feature is important. linux-cross.cpp // DEBIAN_I686_M64-SAME: {{^}} provides an example. But here it may not be important.

asb · 2023-10-27T04:42:04Z

@dtcxzyw Could you please confirm the status of this core - is it commercially available, an academic test chip, something else?

It's maintained by Beijing Institute of Open Source Chip (BOSC), a non-profit organziation founded by companies and researech institutions. It is provided as an open-source CPU Core IP to the third party. It's not an academic testchip.

It's not commercially available now, but there have already been a couple of companies using it as the CPU Core IP. I cannot disclose the progress of commercial chips now but hopefully we will see it soon. There are also some companies using it on FPGAs now.

Thanks for clarifying. We don't really have an established policy here - it's obvious that commercial designs with active support should go in, and that some core design I hacked up over a weekend shouldn't but we haven't had the need to discuss anything in-between that. This patch and the scheduling model aren't large, but if there's thought of adding substantially more specific tuning it might be worth discussing those plans.

All that said, @dtcxzyw this is obviously far from your first patch so I have no concern about support being maintained. @preames suggested that we might want to think about deprecation policy so that we can be fairly liberal in accepting support for new CPUs/microarchs, yet remove them later if they become less relevant. Before you go ahead with the merge, it would be good to confirm that @preames agrees that this patch doesn't need to block on discussing that deprecation policy.

Thanks!

wangpc-pp · 2023-10-27T05:25:02Z

Xiangshan is of great famousness in China and there is already a community in which many individual developers and organiztions/companies like PLCT, T-Head have participated. So I think we needn't worry about the maintenance. :-)

asb · 2023-10-27T16:14:18Z

Xiangshan is of great famousness in China and there is already a community in which many individual developers and organiztions/companies like PLCT, T-Head have participated. So I think we needn't worry about the maintenance. :-)

Thanks for that extra context!

dtcxzyw · 2023-11-01T06:53:04Z

Ping. @preames Any more comments?

Co-authored-by: SForeKeeper <zkliu6@gmail.com>

asb

I think everyone is happy, so please go ahead and squash+merge. Thanks!

dtcxzyw requested review from MaskRay, preames, michaelmaitland, topperc and wangpc-pp October 26, 2023 05:58

dtcxzyw mentioned this pull request Oct 26, 2023

[RISCV] Add sched model for XiangShan-NanHu #70232

Merged

llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Oct 26, 2023

wangpc-pp approved these changes Oct 26, 2023

View reviewed changes

dtcxzyw requested a review from asb October 26, 2023 17:00

MaskRay approved these changes Oct 27, 2023

View reviewed changes

dtcxzyw and others added 2 commits November 1, 2023 14:56

[RISCV] Add processor definition for XiangShan-NanHu

1222b8b

Co-authored-by: SForeKeeper <zkliu6@gmail.com>

fixup! [RISCV] Add processor definition for XiangShan-NanHu

3926358

dtcxzyw force-pushed the xiangshan-proc-def branch from 2903afd to 3926358 Compare November 1, 2023 07:57

asb approved these changes Nov 7, 2023

View reviewed changes

dtcxzyw merged commit 867ece1 into llvm:main Nov 7, 2023
3 checks passed

dtcxzyw deleted the xiangshan-proc-def branch November 7, 2023 16:41

This was referenced Nov 8, 2023

fix empty bb maksfb/llvm-project#2

Closed

fix empty bb maksfb/llvm-project#3

Closed

michaelmaitland mentioned this pull request Jun 10, 2024

[RISCV] Add processor definition for SpacemiT-X60 #94564

Merged

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

[RISCV] Add processor definition for XiangShan-NanHu #70294

[RISCV] Add processor definition for XiangShan-NanHu #70294

dtcxzyw commented Oct 26, 2023

llvmbot commented Oct 26, 2023 •

edited

Loading

wangpc-pp commented Oct 26, 2023

dtcxzyw commented Oct 26, 2023

wangpc-pp left a comment

wangpc-pp Oct 26, 2023

MaskRay Oct 27, 2023

wangpc-pp commented Oct 26, 2023

asb commented Oct 26, 2023

poemonsense commented Oct 26, 2023

poemonsense commented Oct 26, 2023

poemonsense commented Oct 26, 2023

dtcxzyw commented Oct 26, 2023

MaskRay Oct 27, 2023

asb commented Oct 27, 2023

wangpc-pp commented Oct 27, 2023

asb commented Oct 27, 2023

dtcxzyw commented Nov 1, 2023

asb left a comment

[RISCV] Add processor definition for XiangShan-NanHu #70294

[RISCV] Add processor definition for XiangShan-NanHu #70294

Conversation

dtcxzyw commented Oct 26, 2023

llvmbot commented Oct 26, 2023 • edited Loading

wangpc-pp commented Oct 26, 2023

dtcxzyw commented Oct 26, 2023

wangpc-pp left a comment

Choose a reason for hiding this comment

wangpc-pp Oct 26, 2023

Choose a reason for hiding this comment

MaskRay Oct 27, 2023

Choose a reason for hiding this comment

wangpc-pp commented Oct 26, 2023

asb commented Oct 26, 2023

poemonsense commented Oct 26, 2023

poemonsense commented Oct 26, 2023

poemonsense commented Oct 26, 2023

dtcxzyw commented Oct 26, 2023

MaskRay Oct 27, 2023

Choose a reason for hiding this comment

asb commented Oct 27, 2023

wangpc-pp commented Oct 27, 2023

asb commented Oct 27, 2023

dtcxzyw commented Nov 1, 2023

asb left a comment

Choose a reason for hiding this comment

llvmbot commented Oct 26, 2023 •

edited

Loading