[RISCV] Use correct register class for Z[df]inx inline asm

[nemanjai]

Allocate a register of the correct register class for inline asm constraint "r" when used for FP values with -Zfinx/-Zdinx.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Nemanja Ivanovic (nemanjai)

Changes

Allocate a register of the correct register class for inline asm constraint "r" when used for FP values with -Zfinx/-Zdinx.

---

Full diff: https://github.com/llvm/llvm-project/pull/71872.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+4)
• (added) llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll (+43)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8d13563eb138150..1429c9375f1a29b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18370,6 +18370,10 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       // TODO: Support fixed vectors up to XLen for P extension?
       if (VT.isVector())
         break;
+      if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
+        return std::make_pair(0U, &RISCV::GPRF32RegClass);
+      if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
+        return std::make_pair(0U, &RISCV::GPRPF64RegClass);
       return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
     case 'f':
       if (Subtarget.hasStdExtZfhOrZfhmin() && VT == MVT::f16)
diff --git a/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
new file mode 100644
index 000000000000000..ef5c08f80b03426
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck %s
+define dso_local void @zdinx_asm(ptr nocapture noundef writeonly %a, double noundef %b, double noundef %c) nounwind {
+; CHECK-LABEL: zdinx_asm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw a1, 8(sp)
+; CHECK-NEXT:    sw a2, 12(sp)
+; CHECK-NEXT:    lw a6, 8(sp)
+; CHECK-NEXT:    lw a7, 12(sp)
+; CHECK-NEXT:    sw a3, 8(sp)
+; CHECK-NEXT:    sw a4, 12(sp)
+; CHECK-NEXT:    lw a2, 8(sp)
+; CHECK-NEXT:    lw a3, 12(sp)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    fsgnjx.d a2, a6, a2
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    sw a2, 8(a0)
+; CHECK-NEXT:    sw a3, 12(a0)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+entry:
+  %arrayidx = getelementptr inbounds double, ptr %a, i32 1
+  %0 = tail call double asm "fsgnjx.d $0, $1, $2", "=r,r,r"(double %b, double %c)
+  store double %0, ptr %arrayidx, align 8
+  ret void
+}
+
+define dso_local void @zfinx_asm(ptr nocapture noundef writeonly %a, float noundef %b, float noundef %c) nounwind {
+; CHECK-LABEL: zfinx_asm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    fsgnjx.s a1, a1, a2
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    sw a1, 4(a0)
+; CHECK-NEXT:    ret
+entry:
+  %arrayidx = getelementptr inbounds float, ptr %a, i32 1
+  %0 = tail call float asm "fsgnjx.s $0, $1, $2", "=r,r,r"(float %b, float %c)
+  store float %0, ptr %arrayidx, align 8
+  ret void
+}

[topperc]

Is Zhinx broken too?

[nemanjai]

That's a good question. I will try it out later to see.

[nemanjai]

The simple test case for f16 and f32 doesn't cause problems because the necessary physreg copies exist, but I think it's still useful to use the right register class for the respective value.

[topperc]

LGTM