[InstCombine] Infer nneg flag from shift users #71947
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@llvm/pr-subscribers-llvm-transforms Author: Yingwei Zheng (dtcxzyw) ChangesThis patch sets Alive2: https://alive2.llvm.org/ce/z/h3xKjP This is an alternative to #71906. Patch is 31.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/71947.diff 17 Files Affected:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
index c59cf5a2a86ef44..7a59d5d61170e5b 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -1221,9 +1221,18 @@ Instruction *InstCombinerImpl::visitZExt(ZExtInst &Zext) {
}
}
- if (!Zext.hasNonNeg() && isKnownNonNegative(Src, DL, 0, &AC, &Zext, &DT)) {
- Zext.setNonNeg();
- return &Zext;
+ if (!Zext.hasNonNeg()) {
+ // If this zero extend is only used by a shift, add nneg flag.
+ if (Zext.hasOneUse() && SrcTy->getScalarSizeInBits() > 2 &&
+ match(Zext.user_back(), m_Shift(m_Value(), m_Specific(&Zext)))) {
+ Zext.setNonNeg();
+ return &Zext;
+ }
+
+ if (isKnownNonNegative(Src, DL, 0, &AC, &Zext, &DT)) {
+ Zext.setNonNeg();
+ return &Zext;
+ }
}
return nullptr;
diff --git a/llvm/test/Transforms/InstCombine/div-shift.ll b/llvm/test/Transforms/InstCombine/div-shift.ll
index d208837f04594ab..9610746811a43a6 100644
--- a/llvm/test/Transforms/InstCombine/div-shift.ll
+++ b/llvm/test/Transforms/InstCombine/div-shift.ll
@@ -38,7 +38,7 @@ define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
; rdar://11721329
define i64 @t2(i64 %x, i32 %y) {
; CHECK-LABEL: @t2(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y:%.*]] to i64
+; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[Y:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[X:%.*]], [[TMP1]]
; CHECK-NEXT: ret i64 [[TMP2]]
;
@@ -52,7 +52,7 @@ define i64 @t2(i64 %x, i32 %y) {
define i64 @t3(i64 %x, i32 %y) {
; CHECK-LABEL: @t3(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[Y:%.*]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[X:%.*]], [[TMP2]]
; CHECK-NEXT: ret i64 [[TMP3]]
;
diff --git a/llvm/test/Transforms/InstCombine/load-cmp.ll b/llvm/test/Transforms/InstCombine/load-cmp.ll
index 56f6e042b3cafdb..e941284a798ed11 100644
--- a/llvm/test/Transforms/InstCombine/load-cmp.ll
+++ b/llvm/test/Transforms/InstCombine/load-cmp.ll
@@ -122,7 +122,7 @@ define i1 @test4(i32 %X) {
define i1 @test4_i16(i16 %X) {
; CHECK-LABEL: @test4_i16(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i16 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 933, [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP3]], 0
diff --git a/llvm/test/Transforms/InstCombine/rem.ll b/llvm/test/Transforms/InstCombine/rem.ll
index 364d51f343fb3c5..86ef4f45f7da4b6 100644
--- a/llvm/test/Transforms/InstCombine/rem.ll
+++ b/llvm/test/Transforms/InstCombine/rem.ll
@@ -249,7 +249,7 @@ define i32 @test4(i32 %X, i1 %C) {
define i32 @test5(i32 %X, i8 %B) {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext i8 [[B:%.*]] to i32
+; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext nneg i8 [[B:%.*]] to i32
; CHECK-NEXT: [[AMT:%.*]] = shl nuw i32 32, [[SHIFT_UPGRD_1]]
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[AMT]], -1
; CHECK-NEXT: [[V:%.*]] = and i32 [[TMP1]], [[X:%.*]]
diff --git a/llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll b/llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll
index 6910aa5b57a2966..624f06271dcd8ab 100644
--- a/llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll
+++ b/llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll
@@ -73,7 +73,7 @@ define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -90,7 +90,7 @@ define i64 @sel_false_val_is_a_masked_ashr_of_true_val2(i32 %x, i64 %y) {
; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val2(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
diff --git a/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll b/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll
index 7c70178e1bd5170..4bc94d26e875831 100644
--- a/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll
+++ b/llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll
@@ -73,7 +73,7 @@ define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -90,7 +90,7 @@ define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl_nuw__nuw_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -107,7 +107,7 @@ define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl_nsw__nuw_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -124,7 +124,7 @@ define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl__nuw_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -202,7 +202,7 @@ define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -219,7 +219,7 @@ define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl_nuw__none_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -236,7 +236,7 @@ define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl_nsw__none_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -253,7 +253,7 @@ define i64 @test_shl__none_are_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_shl__none_are_safe(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -338,7 +338,7 @@ define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_ashr_exact__exact_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -355,7 +355,7 @@ define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_ashr__exact_is_safe(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -372,7 +372,7 @@ define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
@@ -389,7 +389,7 @@ define i64 @test_ashr__exact_is_unsafe(i32 %x, i64 %y) {
; CHECK-LABEL: @test_ashr__exact_is_unsafe(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
-; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
; CHECK-NEXT: ret i64 [[TMP4]]
;
diff --git a/llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll
index 0fca3dd504bcd75..b26fbad7f973a07 100644
--- a/llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll
@@ -5,7 +5,7 @@
define i32 @shl_C1_add_A_C2_i32(i16 %A) {
; CHECK-LABEL: @shl_C1_add_A_C2_i32(
-; CHECK-NEXT: [[B:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT: [[B:%.*]] = zext nneg i16 [[A:%.*]] to i32
; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
@@ -39,7 +39,7 @@ define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
-; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT: [[B:%.*]] = zext nneg <4 x i16> [[A:%.*]] to <4 x i32>
; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 poison, i32 -458752>, [[B]]
; CHECK-NEXT: ret <4 x i32> [[D]]
;
diff --git a/llvm/test/Transforms/InstCombine/shift-add.ll b/llvm/test/Transforms/InstCombine/shift-add.ll
index 0301b93063385f6..006d303cb56d3c6 100644
--- a/llvm/test/Transforms/InstCombine/shift-add.ll
+++ b/llvm/test/Transforms/InstCombine/shift-add.ll
@@ -7,7 +7,7 @@ declare void @use(i8)
define i32 @shl_C1_add_A_C2_i32(i16 %A) {
; CHECK-LABEL: @shl_C1_add_A_C2_i32(
-; CHECK-NEXT: [[B:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT: [[B:%.*]] = zext nneg i16 [[A:%.*]] to i32
; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
; CHECK-NEXT: ret i32 [[D]]
;
@@ -41,7 +41,7 @@ define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
-; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT: [[B:%.*]] = zext nneg <4 x i16> [[A:%.*]] to <4 x i32>
; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 poison, i32 -458752>, [[B]]
; CHECK-NEXT: ret <4 x i32> [[D]]
;
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
index d48e4ab0d234274..60a7dce2a87534f 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
@@ -19,7 +19,7 @@ define i1 @n0(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -16
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -79,7 +79,7 @@ define i1 @n2(i64 %y, i32 %len) {
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl i32 131071, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -16
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -137,7 +137,7 @@ define i1 @n4(i32 %x, i32 %len) {
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -16
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
; CHECK-NEXT: [[T3:%.*]] = lshr i64 262143, [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -186,7 +186,7 @@ define <2 x i1> @n6_vec(<2 x i64> %y, <2 x i32> %len) {
; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 32, i32 32>, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> <i32 65535, i32 131071>, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -16, i32 -16>
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext <2 x i32> [[T2]] to <2 x i64>
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]
@@ -227,7 +227,7 @@ define <2 x i1> @n8_vec(<2 x i32> %x, <2 x i32> %len) {
; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 32, i32 32>, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -16, i32 -16>
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext <2 x i32> [[T2]] to <2 x i64>
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> <i64 131071, i64 262143>, [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]
@@ -272,7 +272,7 @@ define i1 @t10_almost_highest_bit(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[T0:%.*]] = sub i32 64, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -2
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -314,7 +314,7 @@ define i1 @t10_shift_by_one(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[T0:%.*]] = sub i32 64, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -63
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -338,7 +338,7 @@ define <2 x i1> @t11_zero_and_almost_bitwidth(<2 x i32> %x, <2 x i64> %y, <2 x i
; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 64, i32 64>, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -1, i32 -64>
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext <2 x i32> [[T2]] to <2 x i64>
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]
@@ -360,7 +360,7 @@ define <2 x i1> @n12_bad(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) {
; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 64, i32 64>, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -2, i32 -64>
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext <2 x i32> [[T2]] to <2 x i64>
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
index e49fea4936217c8..3a85f19d8a0375f 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
@@ -400,7 +400,7 @@ define i1 @n13_overshift(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], 32
-; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
+; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
; CHECK-NEXT: [[T3:%.*]] = shl i64 [[Y:%.*]], [[T2_WIDE]]
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -421,7 +421,7 @@ define i1 @n13_overshift(i32 %x, i64 %y, i32 %len) {
define i1 @n14_trunc_of_lshr(i64 %x, i32 %y, i32 %len) {
; CHECK-LABEL: @n14_trunc_of_lshr(
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
-; CHECK-NEXT: [[T0_WIDE:%.*]] = zext i32 [[T0]] to i64
+; CHECK-NEXT: [[T0_WIDE:%.*]] = zext nneg i32 [[T0]] to i64
; CHECK-NEXT: [[T1:%.*]] = lshr i64 [[X:%.*]], [[T0_WIDE]]
; CHECK-NEXT: [[T1_TRUNC:%.*]] = trunc i64 [[T1]] to i32
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -1
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll
index 6c0c6ee0f19dbeb..6773cbac1d1e866 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll
@@ -95,7 +95,7 @@ declare void @use32(i32)
define i16 @t6_extrause0(i32 %x, i16 %y) {
; CHECK-LABEL: @t6_extrause0(
; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
+; CHECK-NEXT: [[T1:%.*]] = zext nneg i16 [[T0]] to i32
; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[X:%.*]], [[T1]]
; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
; CHECK-NEXT: call void @use16(i1...
[truncated]
|
zahiraam
pushed a commit
to zahiraam/llvm-project
that referenced
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Nov 20, 2023
This patch sets `nneg` flag when the zext is only used by a shift. Alive2: https://alive2.llvm.org/ce/z/h3xKjP Compile-time impact: https://llvm-compile-time-tracker.com/compare.php?from=bd611264993f64decbce178d460caf1d1cb05f59&to=26bc473b239010bb24ff1bc39d58b42ecbbc4730&stat=instructions:u This is an alternative to llvm#71906.
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This patch sets
nnegflag when the zext is only used by a shift.Alive2: https://alive2.llvm.org/ce/z/h3xKjP
Compile-time impact: https://llvm-compile-time-tracker.com/compare.php?from=bd611264993f64decbce178d460caf1d1cb05f59&to=26bc473b239010bb24ff1bc39d58b42ecbbc4730&stat=instructions:u
This is an alternative to #71906.