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Hexagon: add support for system instructions #72063

Merged
merged 1 commit into from
Nov 13, 2023
Merged

Hexagon: add support for system instructions #72063

merged 1 commit into from
Nov 13, 2023

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androm3da
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The semantics and encodings for these instructions are described by the Hexagon V67 Programmer's Reference Manual:
https://developer.qualcomm.com/downloads/qualcomm-hexagon-v67-programmer-s-reference-manual

@androm3da androm3da self-assigned this Nov 12, 2023
@llvmbot llvmbot added the mc Machine (object) code label Nov 12, 2023
@llvmbot
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llvmbot commented Nov 12, 2023

@llvm/pr-subscribers-mc

Author: None (androm3da)

Changes

The semantics and encodings for these instructions are described by the Hexagon V67 Programmer's Reference Manual:
https://developer.qualcomm.com/downloads/qualcomm-hexagon-v67-programmer-s-reference-manual

Patch is 86.39 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/72063.diff

4 Files Affected:

  • (modified) llvm/lib/Target/Hexagon/HexagonDepIICScalar.td (+806-2)
  • (modified) llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td (+12)
  • (modified) llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (+401)
  • (added) llvm/test/MC/Hexagon/system-inst.s (+169)
diff --git a/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td b/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td
index 736839bb015b1d8..3bd41767477b33f 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td
@@ -15,6 +15,7 @@ def tc_02fe1c65 : InstrItinClass;
 def tc_0655b949 : InstrItinClass;
 def tc_075c8dd8 : InstrItinClass;
 def tc_0a195f2c : InstrItinClass;
+def tc_0a43be35 : InstrItinClass;
 def tc_0a6c20ae : InstrItinClass;
 def tc_0ba0d5da : InstrItinClass;
 def tc_0dfac0a7 : InstrItinClass;
@@ -62,13 +63,16 @@ def tc_44d5a428 : InstrItinClass;
 def tc_44fffc58 : InstrItinClass;
 def tc_45791fb8 : InstrItinClass;
 def tc_45f9d1be : InstrItinClass;
+def tc_46c18ecf : InstrItinClass;
 def tc_49fdfd4b : InstrItinClass;
 def tc_4a55d03c : InstrItinClass;
 def tc_4abdbdc6 : InstrItinClass;
 def tc_4ac61d92 : InstrItinClass;
 def tc_4bf903b0 : InstrItinClass;
 def tc_503ce0f3 : InstrItinClass;
+def tc_512b1653 : InstrItinClass;
 def tc_53c851ab : InstrItinClass;
+def tc_54f0cee2 : InstrItinClass;
 def tc_5502c366 : InstrItinClass;
 def tc_55255f2b : InstrItinClass;
 def tc_556f6577 : InstrItinClass;
@@ -78,6 +82,7 @@ def tc_56a124a7 : InstrItinClass;
 def tc_57a55b54 : InstrItinClass;
 def tc_5944960d : InstrItinClass;
 def tc_59a7822c : InstrItinClass;
+def tc_5a222e89 : InstrItinClass;
 def tc_5a4b5e58 : InstrItinClass;
 def tc_5b347363 : InstrItinClass;
 def tc_5ceb2f9e : InstrItinClass;
@@ -92,10 +97,12 @@ def tc_651cbe02 : InstrItinClass;
 def tc_65279839 : InstrItinClass;
 def tc_65cbd974 : InstrItinClass;
 def tc_69bfb303 : InstrItinClass;
+def tc_6aa823ab : InstrItinClass;
 def tc_6ae3426b : InstrItinClass;
 def tc_6d861a95 : InstrItinClass;
 def tc_6e20402a : InstrItinClass;
 def tc_6f42bc60 : InstrItinClass;
+def tc_6fb52018 : InstrItinClass;
 def tc_6fc5dbea : InstrItinClass;
 def tc_711c805f : InstrItinClass;
 def tc_713b66bf : InstrItinClass;
@@ -105,11 +112,13 @@ def tc_74a42bda : InstrItinClass;
 def tc_76bb5435 : InstrItinClass;
 def tc_77f94a5e : InstrItinClass;
 def tc_788b1d09 : InstrItinClass;
+def tc_78f87ed3 : InstrItinClass;
 def tc_7af3a37e : InstrItinClass;
 def tc_7b9187d3 : InstrItinClass;
 def tc_7c31e19a : InstrItinClass;
 def tc_7c6d32e4 : InstrItinClass;
 def tc_7dc63b5c : InstrItinClass;
+def tc_7f58404a : InstrItinClass;
 def tc_7f7f45f5 : InstrItinClass;
 def tc_7f8ae742 : InstrItinClass;
 def tc_8035e91f : InstrItinClass;
@@ -134,6 +143,7 @@ def tc_95f43c5e : InstrItinClass;
 def tc_96ef76ef : InstrItinClass;
 def tc_975a4e54 : InstrItinClass;
 def tc_9783714b : InstrItinClass;
+def tc_9b20a062 : InstrItinClass;
 def tc_9b34f5e0 : InstrItinClass;
 def tc_9b3c0462 : InstrItinClass;
 def tc_9bcfb2ee : InstrItinClass;
@@ -152,6 +162,7 @@ def tc_a32e03e7 : InstrItinClass;
 def tc_a38c45dc : InstrItinClass;
 def tc_a4e22bbd : InstrItinClass;
 def tc_a4ee89db : InstrItinClass;
+def tc_a724463d : InstrItinClass;
 def tc_a7a13fac : InstrItinClass;
 def tc_a7bdb22c : InstrItinClass;
 def tc_a9edeffa : InstrItinClass;
@@ -162,11 +173,14 @@ def tc_ae5babd7 : InstrItinClass;
 def tc_aee6250c : InstrItinClass;
 def tc_af6af259 : InstrItinClass;
 def tc_b1ae5f67 : InstrItinClass;
+def tc_b2196a3f : InstrItinClass;
+def tc_b3d46584 : InstrItinClass;
 def tc_b4dc7630 : InstrItinClass;
 def tc_b7c4062a : InstrItinClass;
 def tc_b837298f : InstrItinClass;
 def tc_ba9255a6 : InstrItinClass;
 def tc_bb07f2c5 : InstrItinClass;
+def tc_bb78483e : InstrItinClass;
 def tc_bb831a7c : InstrItinClass;
 def tc_bf2ffc0f : InstrItinClass;
 def tc_c20701f0 : InstrItinClass;
@@ -176,12 +190,14 @@ def tc_c818ff7f : InstrItinClass;
 def tc_ce59038e : InstrItinClass;
 def tc_cfa0e29b : InstrItinClass;
 def tc_d03278fd : InstrItinClass;
+def tc_d234b61a : InstrItinClass;
 def tc_d33e5eee : InstrItinClass;
 def tc_d3632d88 : InstrItinClass;
 def tc_d45ba9cd : InstrItinClass;
 def tc_d57d649c : InstrItinClass;
 def tc_d61dfdc3 : InstrItinClass;
 def tc_d68dca5c : InstrItinClass;
+def tc_d71ea8fa : InstrItinClass;
 def tc_d7718fbe : InstrItinClass;
 def tc_db596beb : InstrItinClass;
 def tc_db96aa6b : InstrItinClass;
@@ -629,6 +645,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT2]>], [2],
       [Hex_FWD]>,
 
+    InstrItinData <tc_46c18ecf, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_49fdfd4b, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
@@ -653,10 +673,18 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_512b1653, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_53c851ab, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_54f0cee2, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
     InstrItinData <tc_5502c366, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -693,6 +721,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_5a222e89, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_5a4b5e58, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -749,6 +781,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_6aa823ab, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_6ae3426b, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
@@ -765,6 +801,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_6fb52018, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_6fc5dbea, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -801,6 +841,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_78f87ed3, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
     InstrItinData <tc_7af3a37e, /*tc_st*/
       [InstrStage<1, [SLOT0]>], [1, 3],
       [Hex_FWD, Hex_FWD]>,
@@ -821,6 +865,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT3]>], [4, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_7f58404a, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
+      []>,
+
     InstrItinData <tc_7f7f45f5, /*tc_3x*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -917,6 +965,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_9b20a062, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_9b34f5e0, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [],
       []>,
@@ -989,6 +1041,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT0]>], [],
       []>,
 
+    InstrItinData <tc_a724463d, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_a7a13fac, /*tc_2early*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1049,6 +1105,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_bb78483e, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_bb831a7c, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1085,6 +1145,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_d234b61a, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
     InstrItinData <tc_d33e5eee, /*tc_2early*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1109,6 +1173,10 @@ class DepScalarItinV55 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_d71ea8fa, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_d7718fbe, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [1],
       [Hex_FWD]>,
@@ -1429,6 +1497,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT2]>], [2],
       [Hex_FWD]>,
 
+    InstrItinData <tc_46c18ecf, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_49fdfd4b, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
@@ -1453,10 +1525,18 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_512b1653, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_53c851ab, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_54f0cee2, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
     InstrItinData <tc_5502c366, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1493,6 +1573,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_5a222e89, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_5a4b5e58, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1549,6 +1633,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_6aa823ab, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_6ae3426b, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
@@ -1565,6 +1653,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_6fb52018, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_6fc5dbea, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1601,6 +1693,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_78f87ed3, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
     InstrItinData <tc_7af3a37e, /*tc_st*/
       [InstrStage<1, [SLOT0]>], [1, 3],
       [Hex_FWD, Hex_FWD]>,
@@ -1621,6 +1717,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_7f58404a, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
+      []>,
+
     InstrItinData <tc_7f7f45f5, /*tc_4x*/
       [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1717,6 +1817,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_9b20a062, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_9b34f5e0, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [],
       []>,
@@ -1789,6 +1893,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT0]>], [],
       []>,
 
+    InstrItinData <tc_a724463d, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_a7a13fac, /*tc_2early*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1849,6 +1957,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_bb78483e, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_bb831a7c, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1885,6 +1997,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_d234b61a, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
     InstrItinData <tc_d33e5eee, /*tc_2early*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -1909,6 +2025,10 @@ class DepScalarItinV60 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_d71ea8fa, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_d7718fbe, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [1],
       [Hex_FWD]>,
@@ -2241,6 +2361,10 @@ class DepScalarItinV60se {
        InstrStage<1, [CVI_ST]>], [2],
       [Hex_FWD]>,
 
+    InstrItinData <tc_46c18ecf, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_49fdfd4b, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
@@ -2265,11 +2389,19 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_512b1653, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_53c851ab, /*tc_2early*/
       [InstrStage<1, [SLOT2], 0>,
        InstrStage<1, [CVI_ST]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_54f0cee2, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
     InstrItinData <tc_5502c366, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3], 0>,
        InstrStage<1, [CVI_ST]>], [3, 2, 2],
@@ -2309,6 +2441,10 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_5a222e89, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_5a4b5e58, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -2367,6 +2503,10 @@ class DepScalarItinV60se {
        InstrStage<1, [CVI_ST]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_6aa823ab, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_6ae3426b, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
@@ -2383,6 +2523,10 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_6fb52018, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_6fc5dbea, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -2420,6 +2564,10 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_78f87ed3, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [],
+      []>,
+
     InstrItinData <tc_7af3a37e, /*tc_st*/
       [InstrStage<1, [SLOT0]>], [1, 3],
       [Hex_FWD, Hex_FWD]>,
@@ -2441,6 +2589,10 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_7f58404a, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [],
+      []>,
+
     InstrItinData <tc_7f7f45f5, /*tc_4x*/
       [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -2539,6 +2691,10 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT2, SLOT3]>], [5, 1],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_9b20a062, /*tc_3stall*/
+      [InstrStage<1, [SLOT2]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_9b34f5e0, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [],
       []>,
@@ -2613,6 +2769,10 @@ class DepScalarItinV60se {
        InstrStage<1, [CVI_ST]>], [],
       []>,
 
+    InstrItinData <tc_a724463d, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_a7a13fac, /*tc_2early*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -2673,6 +2833,10 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_bb78483e, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1, 1],
+      [Hex_FWD, Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_bb831a7c, /*tc_2*/
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -2710,6 +2874,10 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_d234b61a, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1],
+      [Hex_FWD]>,
+
     InstrItinData <tc_d33e5eee, /*tc_2early*/
       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -2735,6 +2903,10 @@ class DepScalarItinV60se {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_d71ea8fa, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [2, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_d7718fbe, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [1],
       [Hex_FWD]>,
@@ -3065,6 +3237,10 @@ class DepScalarItinV62 {
       [InstrStage<1, [SLOT2]>], [2],
       [Hex_FWD]>,
 
+    InstrItinData <tc_46c18ecf, /*tc_3x*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_49fdfd4b, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
@@ -3089,10 +3265,18 @@ class DepScalarItinV62 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_512b1653, /*tc_st*/
+      [InstrStage<1, [SLOT0]>], [1, 2],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_53c851ab, /*tc_2early*/
       [InstrStage<1, [SLOT2]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_54f0cee2, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [1],
+      [Hex_FWD]>,
+
     InstrItinData <tc_5502c366, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -3129,6 +3313,10 @@ class DepScalarItinV62 {
       [InstrStage<1, [SLOT0, SLOT1]>], [1, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_5a222e89, /*tc_2early*/
+      [InstrStage<1, [SLOT2]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_5a4b5e58, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -3185,6 +3373,10 @@ class DepScalarItinV62 {
       [InstrStage<1, [SLOT2, SLOT3]>], [2, 2],
       [Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_6aa823ab, /*tc_3stall*/
+      [InstrStage<1, [SLOT3]>], [4, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_6ae3426b, /*tc_3x*/
       [InstrStage<1, [SLOT3]>], [4, 1],
       [Hex_FWD, Hex_FWD]>,
@@ -3201,6 +3393,10 @@ class DepScalarItinV62 {
       [InstrStage<1, [SLOT0]>], [4, 1, 1],
       [Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_6fb52018, /*tc_3stall*/
+      [InstrStage<1, [SLOT0]>], [1, 1],
+      [Hex_FWD, Hex_FWD]>,
+
     InstrItinData <tc_6fc5dbea, /*tc_1*/
       [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
@@ -3237,6 +3433,10 @@ class DepScalarItinV62 {
       [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2],
       [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
 
+    InstrItinData <tc_78f87ed3, /*tc_3stall*/
+      [InstrStage<1, [S...
[truncated]

@androm3da androm3da changed the title Hexagon: add support for system instrutions Hexagon: add support for system instructions Nov 13, 2023
SundeepKushwaha
SundeepKushwaha approved these changes Nov 13, 2023
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lgtm

@androm3da
Hexagon: add support for system instructions
d5d02b4 
The semantics and encodings for these instructions are described by the
Hexagon V67 Programmer's Reference Manual:
https://developer.qualcomm.com/downloads/qualcomm-hexagon-v67-programmer-s-reference-manual
@androm3da
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This update just now was only to correct the typo in the commit message. s/instrutions/instructions/

@androm3da androm3da merged commit bd91cf8 into llvm:main Nov 13, 2023
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zahiraam pushed a commit to zahiraam/llvm-project that referenced this pull request Nov 20, 2023
@androm3da @zahiraam
Hexagon: add support for system instructions (llvm#72063)
34bb44d 
The semantics and encodings for these instructions are described by the
Hexagon V67 Programmer's Reference Manual:

https://developer.qualcomm.com/downloads/qualcomm-hexagon-v67-programmer-s-reference-manual
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@SidManning SidManning SidManning approved these changes

@SundeepKushwaha SundeepKushwaha SundeepKushwaha approved these changes

@sgundapa sgundapa Awaiting requested review from sgundapa

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