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[RISCV][GISel] Support G_UMIN/UMAX/SMIN/SMAX legal with Zbb. #72182

Merged
merged 4 commits into from
Nov 14, 2023
Merged

[RISCV][GISel] Support G_UMIN/UMAX/SMIN/SMAX legal with Zbb. #72182

merged 4 commits into from
Nov 14, 2023

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topperc
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@topperc topperc commented Nov 14, 2023

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@llvmbot
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llvmbot commented Nov 14, 2023 •
edited

@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-llvm-globalisel

Author: Craig Topper (topperc)

Changes

Patch is 45.75 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/72182.diff

14 Files Affected:

  • (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+9-1)
  • (modified) llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp (+4)
  • (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir (+85)
  • (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir (+82)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir (+54)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir (+54)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir (+44)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umin.mir (+44)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smax.mir (+51)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smin.mir (+51)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umax.mir (+42)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umin.mir (+42)
  • (added) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir (+77)
  • (added) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir (+77)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index c6654873118f98f..c614890dbffd1f3 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -200,7 +200,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
   }
 
   getActionDefinitionsBuilder(G_ABS).lower();
-  getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN}).lower();
+
+  LegalityPredicate HasZbb = [&ST](const LegalityQuery &Query) {
+    return ST.hasStdExtZbb();
+  };
+
+  auto &MinMax = getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN});
+  if (ST.hasStdExtZbb())
+    MinMax.legalFor({sXLen}).minScalar(0, sXLen);
+  MinMax.lower();
 
   getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
 
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index f81ff3e27131bf5..cb1da8ff11c08cb 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -199,9 +199,13 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_SDIV:
   case TargetOpcode::G_SREM:
   case TargetOpcode::G_SMULH:
+  case TargetOpcode::G_SMAX:
+  case TargetOpcode::G_SMIN:
   case TargetOpcode::G_UDIV:
   case TargetOpcode::G_UREM:
   case TargetOpcode::G_UMULH:
+  case TargetOpcode::G_UMAX:
+  case TargetOpcode::G_UMIN:
   case TargetOpcode::G_PTR_ADD:
   case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_INTTOPTR:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir
new file mode 100644
index 000000000000000..b0d387fd640906e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV32I %s
+
+---
+name:            smax_i32
+alignment:       1
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV32I-LABEL: name: smax_i32
+    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT: [[MAX:%[0-9]+]]:gpr = MAX [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[MAX]]
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_SMAX %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            smin_i32
+alignment:       1
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV32I-LABEL: name: smin_i32
+    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT: [[MIN:%[0-9]+]]:gpr = MIN [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[MIN]]
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_SMIN %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            umax_i32
+alignment:       1
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV32I-LABEL: name: umax_i32
+    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT: [[MAXU:%[0-9]+]]:gpr = MAXU [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[MAXU]]
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_UMAX %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            umin_i32
+alignment:       1
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV32I-LABEL: name: umin_i32
+    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV32I-NEXT: [[MINU:%[0-9]+]]:gpr = MINU [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[MINU]]
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = G_UMIN %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir
new file mode 100644
index 000000000000000..4bbe93a4133f651
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir
@@ -0,0 +1,82 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV64I %s
+
+---
+name:            smax_i64
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV64I-LABEL: name: smax_i64
+    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT: [[MAX:%[0-9]+]]:gpr = MAX [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[MAX]]
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_SMAX %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            smin_i64
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV64I-LABEL: name: smin_i64
+    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT: [[MIN:%[0-9]+]]:gpr = MIN [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[MIN]]
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_SMIN %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            umax_i64
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV64I-LABEL: name: umax_i64
+    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT: [[MAXU:%[0-9]+]]:gpr = MAXU [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[MAXU]]
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_UMAX %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            umin_i64
+alignment:       1
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0.entry:
+    ; RV64I-LABEL: name: umin_i64
+    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; RV64I-NEXT: [[MINU:%[0-9]+]]:gpr = MINU [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[MINU]]
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:gprb(s64) = COPY $x10
+    %1:gprb(s64) = COPY $x11
+    %2:gprb(s64) = G_UMIN %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir
index a0833a4b7b550a7..5fcb531567c9099 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir
@@ -1,5 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN:   | FileCheck %s --check-prefix=ZBB
 
 ---
 name:            smax_i8
@@ -21,6 +23,22 @@ body:             |
     ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
     ; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: smax_i8
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+    ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+    ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
+    ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMAX]], [[C2]](s32)
+    ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
+    ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s8) = G_TRUNC %0(s32)
@@ -51,6 +69,22 @@ body:             |
     ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
     ; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: smax_i16
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+    ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+    ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
+    ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMAX]], [[C2]](s32)
+    ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
+    ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s16) = G_TRUNC %0(s32)
@@ -72,6 +106,13 @@ body:             |
     ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: smax_i32
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[COPY1]]
+    ; ZBB-NEXT: $x10 = COPY [[SMAX]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s32) = G_SMAX %0, %1
@@ -95,6 +136,19 @@ body:             |
     ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
     ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: smax_i64
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+    ; ZBB-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+    ; ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
+    ; ZBB-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; ZBB-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+    ; ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+    ; ZBB-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
+    ; ZBB-NEXT: $x10 = COPY [[SELECT1]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s32) = COPY $x12
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir
index e6091ec68b6b269..6622558b7472266 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir
@@ -1,5 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN:   | FileCheck %s --check-prefix=ZBB
 
 ---
 name:            smin_i8
@@ -21,6 +23,22 @@ body:             |
     ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
     ; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: smin_i8
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+    ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+    ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
+    ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMIN]], [[C2]](s32)
+    ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
+    ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s8) = G_TRUNC %0(s32)
@@ -51,6 +69,22 @@ body:             |
     ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
     ; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: smin_i16
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+    ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+    ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
+    ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMIN]], [[C2]](s32)
+    ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
+    ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s16) = G_TRUNC %0(s32)
@@ -72,6 +106,13 @@ body:             |
     ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: smin_i32
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
+    ; ZBB-NEXT: $x10 = COPY [[SMIN]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s32) = G_SMIN %0, %1
@@ -95,6 +136,19 @@ body:             |
     ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
     ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: smin_i64
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+    ; ZBB-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+    ; ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+    ; ZBB-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; ZBB-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+    ; ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+    ; ZBB-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
+    ; ZBB-NEXT: $x10 = COPY [[SELECT1]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s32) = COPY $x12
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir
index a05dd43ce0aa3da..d3e4f2332fa58de 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir
@@ -1,5 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN:   | FileCheck %s --check-prefix=ZBB
 
 ---
 name:            umax_i8
@@ -18,6 +20,17 @@ body:             |
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
     ; CHECK-NEXT: $x10 = COPY [[AND2]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: umax_i8
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+    ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+    ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
+    ; ZBB-NEXT: $x10 = COPY [[UMAX]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s8) = G_TRUNC %0(s32)
@@ -45,6 +58,17 @@ body:             |
     ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
     ; CHECK-NEXT: $x10 = COPY [[AND2]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: umax_i16
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+    ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+    ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
+    ; ZBB-NEXT: $x10 = COPY [[UMAX]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s16) = G_TRUNC %0(s32)
@@ -66,6 +90,13 @@ body:             |
     ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: umax_i32
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]
+    ; ZBB-NEXT: $x10 = COPY [[UMAX]](s32)
+    ; ZBB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s32) = G_UMAX %0, %1
@@ -89,6 +120,19 @@ body:             |
     ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
     ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
     ; CHECK-NEXT: PseudoRET implicit $x10
+    ;
+    ; ZBB-LABEL: name: umax_i64
+    ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; ZBB-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+    ; ZBB-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+    ; ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
+    ; ZBB-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; ZBB-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+    ; ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) ...
[truncated]

michaelmaitland
michaelmaitland reviewed Nov 14, 2023
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llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir Outdated
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=ZBB
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What do you think about adding BOTH,NOZBB and BOTH,ZBB
lines instead of duplicating check lines? I think in this test some of the functions in this test/PR will only use BOTH.

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There should be no duplicates.

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Nevermind, the very last test is duplicate because of the illegal type.

michaelmaitland
michaelmaitland approved these changes Nov 14, 2023
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LGTM.

@topperc topperc merged commit 028ed61 into llvm:main Nov 14, 2023
2 of 3 checks passed
@topperc topperc deleted the pr/gisel-minmax branch November 14, 2023 04:57
zahiraam pushed a commit to zahiraam/llvm-project that referenced this pull request Nov 20, 2023
@topperc @zahiraam
[RISCV][GISel] Support G_UMIN/UMAX/SMIN/SMAX legal with Zbb. (llvm#72182
96b7be9 
)
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@michaelmaitland michaelmaitland michaelmaitland approved these changes

@mshockwave mshockwave Awaiting requested review from mshockwave

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