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[AMDGPU] - Add constant folding to s_wqm intrinsic #72382

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merged 6 commits into from
Nov 21, 2023
Merged

[AMDGPU] - Add constant folding to s_wqm intrinsic #72382

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1864216
[AMDGPU] - Add constant folding to s_wqm intrinsic
OutOfCache Nov 15, 2023
86da1c3
fixup! [AMDGPU] - Add constant folding to s_wqm intrinsic
OutOfCache Nov 15, 2023
08ee504
fixup! [AMDGPU] - Add constant folding to s_wqm intrinsic
OutOfCache Nov 15, 2023
a37a8a9
fixup! [AMDGPU] - Add constant folding to s_wqm intrinsic
OutOfCache Nov 15, 2023
40ee11d
fixup! [AMDGPU] - Add constant folding to s_wqm intrinsic
OutOfCache Nov 17, 2023
fb07847
Merge branch 'main' into wqm-folding
OutOfCache Nov 21, 2023
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10 changes: 10 additions & 0 deletions llvm/lib/Analysis/ConstantFolding.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1533,6 +1533,7 @@ bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
case Intrinsic::amdgcn_perm:
case Intrinsic::amdgcn_wave_reduce_umin:
case Intrinsic::amdgcn_wave_reduce_umax:
case Intrinsic::amdgcn_s_wqm:
case Intrinsic::amdgcn_s_quadmask:
case Intrinsic::amdgcn_s_bitreplicate:
case Intrinsic::arm_mve_vctp8:
Expand Down Expand Up @@ -2425,6 +2426,15 @@ static Constant *ConstantFoldScalarCall1(StringRef Name,
return ConstantFP::get(Ty->getContext(), Val);
}

case Intrinsic::amdgcn_s_wqm: {
uint64_t Val = Op->getZExtValue();
Val |= (Val & 0x5555555555555555ULL) << 1 |
((Val >> 1) & 0x5555555555555555ULL);
Val |= (Val & 0x3333333333333333ULL) << 2 |
((Val >> 2) & 0x3333333333333333ULL);
return ConstantInt::get(Ty, Val);
}

case Intrinsic::amdgcn_s_quadmask: {
uint64_t Val = Op->getZExtValue();
uint64_t QuadMask = 0;
Expand Down
92 changes: 87 additions & 5 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
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Expand Up @@ -9,13 +9,55 @@ define i32 @test_s_wqm_constant_i32() {
; GFX11-LABEL: test_s_wqm_constant_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_wqm_b32 s0, 0x85fe3a92
; GFX11-NEXT: v_mov_b32_e32 v0, 0xff00ff0f
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 u0x85003A02)
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Added zeroes to the constant so it would not just become 0xffffffff. Same thing below.

ret i32 %br
}

define i32 @test_s_wqm_constant_zero_i32() {
; GFX11-LABEL: test_s_wqm_constant_zero_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 0)
ret i32 %br
}

define i32 @test_s_wqm_constant_neg_one_i32() {
; GFX11-LABEL: test_s_wqm_constant_neg_one_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mov_b32_e32 v0, -1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 -1)
ret i32 %br
}

define i32 @test_s_wqm_constant_undef_i32() {
; GFX11-LABEL: test_s_wqm_constant_undef_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_wqm_b32 s0, s0
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 undef)
ret i32 %br
}

define i32 @test_s_wqm_constant_poison_i32() {
; GFX11-LABEL: test_s_wqm_constant_poison_i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_wqm_b32 s0, s0
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 u0x85FE3A92)
%br = call i32 @llvm.amdgcn.s.wqm.i32(i32 poison)
ret i32 %br
}


define amdgpu_cs void @test_s_wqm_sgpr_i32(i32 inreg %mask, ptr addrspace(1) %out) {
; GFX11-LABEL: test_s_wqm_sgpr_i32:
; GFX11: ; %bb.0: ; %entry
Expand Down Expand Up @@ -48,12 +90,52 @@ define i64 @test_s_wqm_constant_i64() {
; GFX11-LABEL: test_s_wqm_constant_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0x85fe3a92
; GFX11-NEXT: s_mov_b32 s1, 0x3a9285fe
; GFX11-NEXT: v_mov_b32_e32 v0, 0xff00ffff
; GFX11-NEXT: v_mov_b32_e32 v1, 0xffff0fff
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i64 @llvm.amdgcn.s.wqm.i64(i64 u0x12480FDBAC00753E)
ret i64 %br
}

define i64 @test_s_wqm_constant_zero_i64() {
; GFX11-LABEL: test_s_wqm_constant_zero_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i64 @llvm.amdgcn.s.wqm.i64(i64 0)
ret i64 %br
}

define i64 @test_s_wqm_constant_neg_one_i64() {
; GFX11-LABEL: test_s_wqm_constant_neg_one_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, -1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i64 @llvm.amdgcn.s.wqm.i64(i64 -1)
ret i64 %br
}

define i64 @test_s_wqm_constant_undef_i64() {
; GFX11-LABEL: test_s_wqm_constant_undef_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_wqm_b64 s[0:1], s[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i64 @llvm.amdgcn.s.wqm.i64(i64 undef)
ret i64 %br
}

define i64 @test_s_wqm_constant_poison_i64() {
; GFX11-LABEL: test_s_wqm_constant_poison_i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_wqm_b64 s[0:1], s[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%br = call i64 @llvm.amdgcn.s.wqm.i64(i64 u0x3A9285FE85FE3A92)
%br = call i64 @llvm.amdgcn.s.wqm.i64(i64 poison)
ret i64 %br
}

Expand Down