[PowerPC] Add a set of extended mnemonics that are missing from Power 10. #73003
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stefanp-ibm
requested review from
ecnelises,
nemanjai,
amy-kwan,
mandlebug and
lei137
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@llvm/pr-subscribers-mc Author: Stefan Pintilie (stefanp-ibm) ChangesThis patch adds the majority of the missing extended mnemonics that were introduced in Power 10. The only extended mnemonics that were not added are related to the plq and pstq instructions. These will be added in a separate patch as the instructions themselves would also have to be added. Patch is 53.91 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73003.diff 11 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index ed52b9a9cf27b7b..fa11e071fb50642 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -820,6 +820,27 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
const OperandVector &Operands) {
int Opcode = Inst.getOpcode();
switch (Opcode) {
+ case PPC::PLA8:
+ case PPC::PLA: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(PPC::PADDI);
+ TmpInst.setOpcode(Opcode == PPC::PLA ? PPC::PADDI : PPC::PADDI8);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ TmpInst.addOperand(Inst.getOperand(2));
+ Inst = TmpInst;
+ break;
+ }
+ case PPC::PLA8pc:
+ case PPC::PLApc: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(Opcode == PPC::PLApc ? PPC::PADDIpc : PPC::PADDI8pc);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(MCOperand::createImm(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ Inst = TmpInst;
+ break;
+ }
case PPC::DCBTx:
case PPC::DCBTT:
case PPC::DCBTSTx:
@@ -895,6 +916,15 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
Inst = TmpInst;
break;
}
+ case PPC::PSUBI: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(PPC::PADDI);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ addNegOperand(TmpInst, Inst.getOperand(2), getContext());
+ Inst = TmpInst;
+ break;
+ }
case PPC::SUBIS: {
MCInst TmpInst;
TmpInst.setOpcode(PPC::ADDIS);
@@ -1226,7 +1256,6 @@ bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
MCInst Inst;
-
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
case Match_Success:
// Post-process instructions (typically extended mnemonics)
diff --git a/llvm/lib/Target/PowerPC/P10InstrResources.td b/llvm/lib/Target/PowerPC/P10InstrResources.td
index 66a050955631a78..3bbc5a63ca7abe8 100644
--- a/llvm/lib/Target/PowerPC/P10InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -875,7 +875,7 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY],
MCRXRX,
MFCTR, MFCTR8,
MFLR, MFLR8,
- WAIT
+ WAIT, WAITP10
)>;
// 3 Cycles ALU operations, 1 input operands
@@ -1884,6 +1884,7 @@ def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read,
def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY],
(instrs
ISYNC,
+ SYNCP10,
SYNC
)>;
diff --git a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
index 5d97d187b2969a3..8bbe315a2bb9a74 100644
--- a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
+++ b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
@@ -958,6 +958,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
V_SET0B,
V_SET0H,
WAIT,
+ WAITP10,
XOR,
XOR8,
XOR8_rec,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 6501c17dd810e64..30693cd64fcc4a9 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -725,6 +725,38 @@ class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Inst{31} = 0;
}
+class XForm_24_P10wait<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<2> L;
+ bits<2> PL;
+
+ let Pattern = pattern;
+ let Inst{6-8} = 0;
+ let Inst{9-10} = L;
+ let Inst{11-13} = 0;
+ let Inst{14-15} = PL;
+ let Inst{16-20} = 0;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+class XForm_24_P10sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<3> L;
+ bits<2> SC;
+
+ let Pattern = pattern;
+ let Inst{6-7} = 0;
+ let Inst{8-10} = L;
+ let Inst{11-13} = 0;
+ let Inst{14-15} = SC;
+ let Inst{16-20} = 0;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index a97062e0c643fb2..6199785206b2f76 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3437,6 +3437,23 @@ def crnot : OutPatFrag<(ops node:$in),
def : Pat<(not i1:$in),
(crnot $in)>;
+// Pseudo-instructions for alternate assembly syntax (never used by codegen).
+// These are aliases that require C++ handling to convert to the target
+// instruction, while InstAliases can be handled directly by tblgen.
+class PPCAsmPseudo<string asm, dag iops>
+ : Instruction {
+ let Namespace = "PPC";
+ bit PPC64 = 0; // Default value, override with isPPC64
+
+ let OutOperandList = (outs);
+ let InOperandList = iops;
+ let Pattern = [];
+ let AsmString = asm;
+ let isAsmParserOnly = 1;
+ let isPseudo = 1;
+ let hasNoSchedulingInfo = 1;
+}
+
// Prefixed instructions may require access to the above defs at a later
// time so we include this after the def.
include "PPCInstrP10.td"
@@ -4458,23 +4475,6 @@ def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $a
// PowerPC Assembler Instruction Aliases
//
-// Pseudo-instructions for alternate assembly syntax (never used by codegen).
-// These are aliases that require C++ handling to convert to the target
-// instruction, while InstAliases can be handled directly by tblgen.
-class PPCAsmPseudo<string asm, dag iops>
- : Instruction {
- let Namespace = "PPC";
- bit PPC64 = 0; // Default value, override with isPPC64
-
- let OutOperandList = (outs);
- let InOperandList = iops;
- let Pattern = [];
- let AsmString = asm;
- let isAsmParserOnly = 1;
- let isPseudo = 1;
- let hasNoSchedulingInfo = 1;
-}
-
def : InstAlias<"sc", (SC 0)>;
def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index a5429b38dfbe2d6..a0de5f8df4a96c5 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -575,33 +575,54 @@ class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
}
multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
+ dag PCRel_IOL, dag PCRelOnly_IOL,
+ string asmstr, string asmstrpc,
InstrItinClass itin> {
def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>;
def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>,
isPCRel;
+ let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
+ def nopc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
+ let RA = 0 in
+ def onlypc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,
+ asmstrpc, itin, []>, isPCRel;
+ }
}
multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
+ dag PCRel_IOL, dag PCRelOnly_IOL,
+ string asmstr, string asmstrpc,
InstrItinClass itin> {
def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>;
def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>,
isPCRel;
+ let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
+ def nopc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
+ let RA = 0 in
+ def onlypc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,
+ asmstrpc, itin, []>, isPCRel;
+ }
}
multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
- dag PCRel_IOL, string asmstr,
+ dag PCRel_IOL, dag PCRelOnly_IOL,
+ string asmstr, string asmstrpc,
InstrItinClass itin> {
def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL,
!strconcat(asmstr, ", 0"), itin, []>;
def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL,
!strconcat(asmstr, ", 1"), itin, []>,
isPCRel;
+ let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
+ def nopc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
+ let RA = 0 in
+ def onlypc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRelOnly_IOL,
+ asmstrpc, itin, []>, isPCRel;
+ }
}
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
@@ -615,7 +636,7 @@ def RCCp {
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PADDI8 :
- MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
+ MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm:$SI),
(ins immZero:$RA, s34imm_pcrel:$SI),
"paddi $RT, $RA, $SI", IIC_LdStLFD>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
@@ -625,7 +646,7 @@ let Predicates = [PrefixInstrs] in {
}
}
defm PADDI :
- MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
+ MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc_nor0:$RA, s34imm:$SI),
(ins immZero:$RA, s34imm_pcrel:$SI),
"paddi $RT, $RA, $SI", IIC_LdStLFD>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
@@ -638,68 +659,88 @@ let Predicates = [PrefixInstrs] in {
defm PLXV :
8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- "plxv $XST, $addr", IIC_LdStLFD>;
+ (ins s34imm_pcrel:$D),
+ "plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>;
defm PLFS :
MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plfs $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plfs $RST, $addr",
+ "plfs $RST, $D", IIC_LdStLFD>;
defm PLFD :
MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plfd $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plfd $RST, $addr",
+ "plfd $RST, $D", IIC_LdStLFD>;
defm PLXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- "plxssp $RST, $addr", IIC_LdStLFD>;
+ (ins s34imm_pcrel:$D),
+ "plxssp $RST, $addr", "plxssp $RST, $D",
+ IIC_LdStLFD>;
defm PLXSD :
8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- "plxsd $RST, $addr", IIC_LdStLFD>;
+ (ins s34imm_pcrel:$D),
+ "plxsd $RST, $addr", "plxsd $RST, $D",
+ IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PLBZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plbz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plbz $RST, $addr",
+ "plbz $RST, $D", IIC_LdStLFD>;
defm PLHZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plhz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plhz $RST, $addr",
+ "plhz $RST, $D", IIC_LdStLFD>;
defm PLHA8 :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plha $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plha $RST, $addr",
+ "plha $RST, $D", IIC_LdStLFD>;
defm PLWA8 :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- "plwa $RST, $addr", IIC_LdStLFD>;
+ (ins s34imm_pcrel:$D),
+ "plwa $RST, $addr", "plwa $RST, $D", IIC_LdStLFD>;
defm PLWZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plwz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plwz $RST, $addr",
+ "plwz $RST, $D", IIC_LdStLFD>;
}
defm PLBZ :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plbz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plbz $RST, $addr",
+ "plbz $RST, $D", IIC_LdStLFD>;
defm PLHZ :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plhz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plhz $RST, $addr",
+ "plhz $RST, $D", IIC_LdStLFD>;
defm PLHA :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plha $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plha $RST, $addr",
+ "plha $RST, $D", IIC_LdStLFD>;
defm PLWZ :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plwz $RST, $addr",
- IIC_LdStLFD>;
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D), "plwz $RST, $addr",
+ "plwz $RST, $D", IIC_LdStLFD>;
defm PLWA :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "plwa $RST, $addr",
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D),
+ "plwa $RST, $addr", "plwa $RST, $D",
IIC_LdStLFD>;
defm PLD :
8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
- (ins (memri34_pcrel $D, $RA):$addr), "pld $RST, $addr",
+ (ins (memri34_pcrel $D, $RA):$addr),
+ (ins s34imm_pcrel:$D),
+ "pld $RST, $addr", "pld $RST, $D",
IIC_LdStLFD>;
}
@@ -707,53 +748,65 @@ let Predicates = [PrefixInstrs] in {
defm PSTXV :
8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
(ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
- "pstxv $XST, $addr", IIC_LdStLFD>;
+ (ins vsrc:$XST, s34imm_pcrel:$D),
+ "pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>;
defm PSTFS :
MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
(ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstfs $RST, $addr", IIC_LdStLFD>;
+ (ins f4rc:$RST, s34imm_pcrel:$D),
+ "pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>;
defm PSTFD :
MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
(ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstfd $RST, $addr", IIC_LdStLFD>;
+ (ins f8rc:$RST, s34imm_pcrel:$D),
+ "pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>;
defm PSTXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstxssp $RST, $addr", IIC_LdStLFD>;
+ (ins vfrc:$RST, s34imm_pcrel:$D),
+ "pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>;
defm PSTXSD :
8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
- "pstxsd $RST, $addr", IIC_LdStLFD>;
+ (ins vfrc:$RST, s34imm_pcrel:$D),
+ "pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PSTB8 :
MLS_DForm_R_SI34_RTA...
[truncated]
|
lei137
reviewed
Nov 23, 2023
| TmpInst.addOperand(Inst.getOperand(1)); | ||
| Inst = TmpInst; | ||
| break; | ||
| } |
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nit: would it make sense to move these lower to where we handle PPC:LA?
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Sure, I can move these down. I guess I just added them to the top.
| let isPseudo = 1; | ||
| let hasNoSchedulingInfo = 1; | ||
| } | ||
|
|
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This look like just a move of a prev def. Any reason that this was needed?
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Is it because we need access to stuff like isAsmParserOnly and hasNoSchedulingInfo inside PPCInstrP10.td, as well?
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Yes. I moved that up because I needed it for this line:
def PSUBI : PPCAsmPseudo<"psubi $RT, $RA, $SI",
so I had to move it before include "PPCInstrP10.td".
| @@ -53,8 +53,8 @@ | |||
| wait 4 | |||
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| # CHECK: error: invalid operand for instruction | |||
| # CHECK-NEXT: sync 4 | |||
| sync 4 | |||
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Yes this is unfortunately required. On Power 10 we now have 3 bits instead of just 2 bits for the sync instruction and therefore a value of 4 for the argument is now valid. In order for this test to make sure that we get the invalid instruction we need a value that doesn't fit in 3 bits.
| @@ -725,6 +725,38 @@ class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, | |||
| let Inst{31} = 0; | |||
| } | |||
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| class XForm_24_P10wait<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, | |||
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Most of these classes don't have the instruction name ref in it. Any specific reason why these do instead of following the newly setup instr class naming convention?
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So, the original wait instruction was called XForm_24_sync and it was used both for sync and for wait. Now that the wait instruction has changed I added the P10wait so that it looks related to the other instruction.
However, I'm not attached to this name so I will change it.
amy-kwan
reviewed
Nov 23, 2023
| case PPC::PLA8: | ||
| case PPC::PLA: { | ||
| MCInst TmpInst; | ||
| TmpInst.setOpcode(PPC::PADDI); |
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Is this line needed if we are going to end up setting the opcode below on 827 anyway?
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Ooops. Good catch.
I missed deleting that.
| let isPseudo = 1; | ||
| let hasNoSchedulingInfo = 1; | ||
| } | ||
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|
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Is it because we need access to stuff like isAsmParserOnly and hasNoSchedulingInfo inside PPCInstrP10.td, as well?
nemanjai
approved these changes
Nov 26, 2023
| @@ -615,7 +636,7 @@ def RCCp { | |||
| let Predicates = [PrefixInstrs] in { | |||
| let Interpretation64Bit = 1, isCodeGenOnly = 1 in { | |||
| defm PADDI8 : | |||
| MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI), | |||
| MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm:$SI), | |||
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This and line 649 appear to be bug fixes. If so, I think they should go into a separate commit.
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Yes, this is a bug fix.
I will move this to another patch (#73995)
| } | ||
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| multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, | ||
| dag PCRel_IOL, string asmstr, | ||
| dag PCRel_IOL, dag PCRelOnly_IOL, | ||
| string asmstr, string asmstrpc, |
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I'm not crazy about the name asmstrpc since this multiclass defines 4 instructions (2 non-pcrel and 2 pcrel) and we use asmstrpc for only one of the pcrel ones. Perhaps asmstr_pcext because this is for the extended mnemonics.
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I will change the name.
| # CHECK-BE-SAME: 0x38,0x80,0x00,0x18] | ||
| # CHECK-LE: paddi 4, 0, 24, 1 # encoding: [0x00,0x00,0x10,0x06, | ||
| # CHECK-LE-SAME: 0x18,0x00,0x80,0x38] | ||
| pla 4, 24 |
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Please choose immediates that are larger than the number of registers (probably useful to make them larger than the values that fit in traditional immediate fields of 16 bits).
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I will change the immediate values to force the instruction to use more than 16 bits.
I'm going to use 4294965249 = fffff801
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… 10. This patch adds the majority of the missing extended mnemonics that were introduced in Power 10. The only extended menemonics that were not added are related to the plq and pstq instructions. These will be added in a separate patch as the instructions themselves would also have to be added.
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This patch adds the majority of the missing extended mnemonics that were introduced in Power 10.
The only extended mnemonics that were not added are related to the plq and pstq instructions. These will be added in a separate patch as the instructions themselves would also have to be added.