[X86][MC] Allow to specify any of the 8/16/32/64 register names interchangeably for R16-R31 #73421
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…changeably for R16-R31
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@llvm/pr-subscribers-backend-x86 Author: Shengchen Kan (KanRobert) ChangesFull diff: https://github.com/llvm/llvm-project/pull/73421.diff 2 Files Affected:
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index af5cb1215abcce8..3b4638afeaf11a5 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -817,6 +817,22 @@ MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
NO_SUB_SUPER(13, R13B)
NO_SUB_SUPER(14, R14B)
NO_SUB_SUPER(15, R15B)
+ NO_SUB_SUPER(16, R16B)
+ NO_SUB_SUPER(17, R17B)
+ NO_SUB_SUPER(18, R18B)
+ NO_SUB_SUPER(19, R19B)
+ NO_SUB_SUPER(20, R20B)
+ NO_SUB_SUPER(21, R21B)
+ NO_SUB_SUPER(22, R22B)
+ NO_SUB_SUPER(23, R23B)
+ NO_SUB_SUPER(24, R24B)
+ NO_SUB_SUPER(25, R25B)
+ NO_SUB_SUPER(26, R26B)
+ NO_SUB_SUPER(27, R27B)
+ NO_SUB_SUPER(28, R28B)
+ NO_SUB_SUPER(29, R29B)
+ NO_SUB_SUPER(30, R30B)
+ NO_SUB_SUPER(31, R31B)
}
}
case 16:
@@ -838,6 +854,22 @@ MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
NO_SUB_SUPER(13, R13W)
NO_SUB_SUPER(14, R14W)
NO_SUB_SUPER(15, R15W)
+ NO_SUB_SUPER(16, R16W)
+ NO_SUB_SUPER(17, R17W)
+ NO_SUB_SUPER(18, R18W)
+ NO_SUB_SUPER(19, R19W)
+ NO_SUB_SUPER(20, R20W)
+ NO_SUB_SUPER(21, R21W)
+ NO_SUB_SUPER(22, R22W)
+ NO_SUB_SUPER(23, R23W)
+ NO_SUB_SUPER(24, R24W)
+ NO_SUB_SUPER(25, R25W)
+ NO_SUB_SUPER(26, R26W)
+ NO_SUB_SUPER(27, R27W)
+ NO_SUB_SUPER(28, R28W)
+ NO_SUB_SUPER(29, R29W)
+ NO_SUB_SUPER(30, R30W)
+ NO_SUB_SUPER(31, R31W)
}
case 32:
switch (Reg.id()) {
@@ -858,6 +890,22 @@ MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
NO_SUB_SUPER(13, R13D)
NO_SUB_SUPER(14, R14D)
NO_SUB_SUPER(15, R15D)
+ NO_SUB_SUPER(16, R16D)
+ NO_SUB_SUPER(17, R17D)
+ NO_SUB_SUPER(18, R18D)
+ NO_SUB_SUPER(19, R19D)
+ NO_SUB_SUPER(20, R20D)
+ NO_SUB_SUPER(21, R21D)
+ NO_SUB_SUPER(22, R22D)
+ NO_SUB_SUPER(23, R23D)
+ NO_SUB_SUPER(24, R24D)
+ NO_SUB_SUPER(25, R25D)
+ NO_SUB_SUPER(26, R26D)
+ NO_SUB_SUPER(27, R27D)
+ NO_SUB_SUPER(28, R28D)
+ NO_SUB_SUPER(29, R29D)
+ NO_SUB_SUPER(30, R30D)
+ NO_SUB_SUPER(31, R31D)
}
case 64:
switch (Reg.id()) {
@@ -878,6 +926,22 @@ MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,
NO_SUB_SUPER(13, R13)
NO_SUB_SUPER(14, R14)
NO_SUB_SUPER(15, R15)
+ NO_SUB_SUPER(16, R16)
+ NO_SUB_SUPER(17, R17)
+ NO_SUB_SUPER(18, R18)
+ NO_SUB_SUPER(19, R19)
+ NO_SUB_SUPER(20, R20)
+ NO_SUB_SUPER(21, R21)
+ NO_SUB_SUPER(22, R22)
+ NO_SUB_SUPER(23, R23)
+ NO_SUB_SUPER(24, R24)
+ NO_SUB_SUPER(25, R25)
+ NO_SUB_SUPER(26, R26)
+ NO_SUB_SUPER(27, R27)
+ NO_SUB_SUPER(28, R28)
+ NO_SUB_SUPER(29, R29)
+ NO_SUB_SUPER(30, R30)
+ NO_SUB_SUPER(31, R31)
}
}
}
diff --git a/llvm/test/CodeGen/X86/asm-mismatched-types.ll b/llvm/test/CodeGen/X86/asm-mismatched-types.ll
index 97f9c0872f8f50d..47525e025f1dc37 100644
--- a/llvm/test/CodeGen/X86/asm-mismatched-types.ll
+++ b/llvm/test/CodeGen/X86/asm-mismatched-types.ll
@@ -133,3 +133,129 @@ define void @reg8_as_16(i16 %p) {
call void asm sideeffect "# REG: $0", "{dil}"(i16 %p)
ret void
}
+
+; CHECK-LABEL: egpr_reg64_as_32:
+; CHECK: # REG: %r16d
+define void @egpr_reg64_as_32(i32 %p) {
+ call void asm sideeffect "# REG: $0", "{r16}"(i32 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg64_as_32_float:
+; CHECK: # REG: %r16d
+define void @egpr_reg64_as_32_float(float %p) {
+ call void asm sideeffect "# REG: $0", "{r16}"(float %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg64_as_16:
+; CHECK: # REG: %r17w
+define void @egpr_reg64_as_16(i16 %p) {
+ call void asm sideeffect "# REG: $0", "{r17}"(i16 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg64_as_8:
+; CHECK: # REG: %r21b
+define void @egpr_reg64_as_8(i8 %p) {
+ call void asm sideeffect "# REG: $0", "{r21}"(i8 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg32_as_16:
+; CHECK: # REG: %r21w
+define void @egpr_reg32_as_16(i16 %p) {
+ call void asm sideeffect "# REG: $0", "{r21d}"(i16 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg32_as_8:
+; CHECK: # REG: %r20b
+define void @egpr_reg32_as_8(i8 %p) {
+ call void asm sideeffect "# REG: $0", "{r20d}"(i8 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg16_as_8:
+; CHECK: # REG: %r17b
+define void @egpr_reg16_as_8(i8 %p) {
+ call void asm sideeffect "# REG: $0", "{r17w}"(i8 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg32_as_64:
+; CHECK: # REG: %r21
+define void @egpr_reg32_as_64(i64 %p) {
+ call void asm sideeffect "# REG: $0", "{r21d}"(i64 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg32_as_64_float:
+; CHECK: # REG: %r21
+define void @egpr_reg32_as_64_float(double %p) {
+ call void asm sideeffect "# REG: $0", "{r21d}"(double %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg16_as_64:
+; CHECK: # REG: %r21
+define void @egpr_reg16_as_64(i64 %p) {
+ call void asm sideeffect "# REG: $0", "{r21w}"(i64 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg16_as_64_float:
+; CHECK: # REG: %r21
+define void @egpr_reg16_as_64_float(double %p) {
+ call void asm sideeffect "# REG: $0", "{r21w}"(double %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg8_as_64:
+; CHECK: # REG: %r16
+define void @egpr_reg8_as_64(i64 %p) {
+ call void asm sideeffect "# REG: $0", "{r16b}"(i64 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg8_as_64_float:
+; CHECK: # REG: %r16
+define void @egpr_reg8_as_64_float(double %p) {
+ call void asm sideeffect "# REG: $0", "{r16b}"(double %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg16_as_32:
+; CHECK: # REG: %r19d
+define void @egpr_reg16_as_32(i32 %p) {
+ call void asm sideeffect "# REG: $0", "{r19w}"(i32 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg16_as_32_float:
+; CHECK: # REG: %r19d
+define void @egpr_reg16_as_32_float(float %p) {
+ call void asm sideeffect "# REG: $0", "{r19w}"(float %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg8_as_32:
+; CHECK: # REG: %r17d
+define void @egpr_reg8_as_32(i32 %p) {
+ call void asm sideeffect "# REG: $0", "{r17b}"(i32 %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg8_as_32_float:
+; CHECK: # REG: %r17d
+define void @egpr_reg8_as_32_float(float %p) {
+ call void asm sideeffect "# REG: $0", "{r17b}"(float %p)
+ ret void
+}
+
+; CHECK-LABEL: egpr_reg8_as_16:
+; CHECK: # REG: %r18w
+define void @egpr_reg8_as_16(i16 %p) {
+ call void asm sideeffect "# REG: $0", "{r18b}"(i16 %p)
+ ret void
+}
|
KanRobert
requested review from
RKSimon,
phoebewang,
e-kud,
topperc and
XinWang10
phoebewang
reviewed
Nov 26, 2023
| @@ -817,6 +817,22 @@ MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size, | |||
| NO_SUB_SUPER(13, R13B) | |||
| NO_SUB_SUPER(14, R14B) | |||
| NO_SUB_SUPER(15, R15B) | |||
| NO_SUB_SUPER(16, R16B) | |||
There was a problem hiding this comment.
How about define a NO_SUB_SUPERB(8)?
There was a problem hiding this comment.
Good suggestion. Done.
|
Thanks @phoebewang @XinWang10 |
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