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[RISCV] Generate bexti for (select(setcc eq (and x, c))) where c is power of 2. #73649

Merged
merged 3 commits into from
Nov 29, 2023
Merged

[RISCV] Generate bexti for (select(setcc eq (and x, c))) where c is power of 2. #73649

merged 3 commits into from
Nov 29, 2023
+317 −190

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yetingk
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@yetingk yetingk commented Nov 28, 2023

Currently, llvm can transform (setcc ne (and x, c)) to (bexti x, log2(c)) where c is power of 2.
This patch transform (select (setcc ne (and x, c)), T, F) into (select (setcc eq (and x, c)), F, T).
It is benefit to the case c is not fit to 12-bits.

@yetingk
[RISCV] Precommit test.
41619ca
@yetingk
[RISCV] Generate bexti for (setcc eq (and x, c)) where c is power of 2.
396f84b 
Currently, llvm can transform (setcc ne (and x, c)) to (bexti x, log2(c)) where
c is power of 2.
This patch transform (select (setcc ne (and x, c)), T, F) into (select (setcc eq (and x, c)), F, T).
It is benefit to the case c is not fit to 12-bits.
@llvmbot
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llvmbot commented Nov 28, 2023

@llvm/pr-subscribers-backend-risc-v

Author: Yeting Kuo (yetingk)

Changes

Currently, llvm can transform (setcc ne (and x, c)) to (bexti x, log2(c)) where c is power of 2.
This patch transform (select (setcc ne (and x, c)), T, F) into (select (setcc eq (and x, c)), F, T).
It is benefit to the case c is not fit to 12-bits.

Patch is 41.13 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73649.diff

2 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+32)
  • (modified) llvm/test/CodeGen/RISCV/condops.ll (+286-193)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a417b6fe05e59df..0e4939318b27490 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14182,11 +14182,43 @@ static SDValue foldSelectOfCTTZOrCTLZ(SDNode *N, SelectionDAG &DAG) {
   return DAG.getZExtOrTrunc(AndNode, SDLoc(N), N->getValueType(0));
 }
 
+static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG,
+                                const RISCVSubtarget &Subtarget) {
+  SDValue Cond = N->getOperand(0);
+  SDValue True = N->getOperand(1);
+  SDValue False = N->getOperand(2);
+  SDLoc DL(N);
+  EVT VT = N->getValueType(0);
+  EVT CondVT = Cond.getValueType();
+
+  if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
+    return SDValue();
+
+  // Replace (setcc eq (and x, C)) with (setcc ne (and x, C))) to generate
+  // BEXTI, where C is power of 2.
+  if (Subtarget.hasStdExtZbs() && VT.isScalarInteger() &&
+      (Subtarget.hasStdExtZicond() || Subtarget.hasVendorXVentanaCondOps())) {
+    SDValue LHS = Cond.getOperand(0);
+    SDValue RHS = Cond.getOperand(1);
+    ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
+    if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND &&
+        isa<ConstantSDNode>(LHS.getOperand(1)) &&
+        cast<ConstantSDNode>(LHS.getOperand(1))->getAPIntValue().isPowerOf2() &&
+        isNullConstant(RHS))
+      return DAG.getSelect(
+          DL, VT, DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE), False, True);
+  }
+  return SDValue();
+}
+
 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
                                     const RISCVSubtarget &Subtarget) {
   if (SDValue Folded = foldSelectOfCTTZOrCTLZ(N, DAG))
     return Folded;
 
+  if (SDValue V = useInversedSetcc(N, DAG, Subtarget))
+    return V;
+
   if (Subtarget.hasShortForwardBranchOpt())
     return SDValue();
 
diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll
index b9912c6ccfb98cd..97ba53a41ede4ec 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f < %s | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f < %s | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
-; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
-; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
+; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
+; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
 
 define i64 @zero1(i64 %rs1, i1 zeroext %rc) {
 ; RV32I-LABEL: zero1:
@@ -82,6 +82,104 @@ define i64 @zero2(i64 %rs1, i1 zeroext %rc) {
   ret i64 %sel
 }
 
+define i64 @zero_singlebit1(i64 %rs1, i64 %rs2) {
+; RV32I-LABEL: zero_singlebit1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bexti a2, a2, 12
+; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: zero_singlebit1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    bexti a1, a1, 12
+; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: zero_singlebit1:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    bexti a1, a1, 12
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a0, a1
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: zero_singlebit1:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    lui a2, 1
+; RV64XTHEADCONDMOV-NEXT:    and a1, a1, a2
+; RV64XTHEADCONDMOV-NEXT:    th.mvnez a0, zero, a1
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero_singlebit1:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    bexti a2, a2, 12
+; RV32ZICOND-NEXT:    czero.nez a0, a0, a2
+; RV32ZICOND-NEXT:    czero.nez a1, a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero_singlebit1:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    bexti a1, a1, 12
+; RV64ZICOND-NEXT:    czero.nez a0, a0, a1
+; RV64ZICOND-NEXT:    ret
+  %and = and i64 %rs2, 4096
+  %rc = icmp eq i64 %and, 0
+  %sel = select i1 %rc, i64 %rs1, i64 0
+  ret i64 %sel
+}
+
+; TODO: Optimize Zicond case.
+define i64 @zero_singlebit2(i64 %rs1, i64 %rs2) {
+; RV32I-LABEL: zero_singlebit2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a2, a2, 19
+; RV32I-NEXT:    srai a2, a2, 31
+; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: zero_singlebit2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a1, a1, 51
+; RV64I-NEXT:    srai a1, a1, 63
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: zero_singlebit2:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    slli a1, a1, 51
+; RV64XVENTANACONDOPS-NEXT:    srai a1, a1, 63
+; RV64XVENTANACONDOPS-NEXT:    and a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: zero_singlebit2:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    slli a1, a1, 51
+; RV64XTHEADCONDMOV-NEXT:    srai a1, a1, 63
+; RV64XTHEADCONDMOV-NEXT:    and a0, a1, a0
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: zero_singlebit2:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    slli a2, a2, 19
+; RV32ZICOND-NEXT:    srai a2, a2, 31
+; RV32ZICOND-NEXT:    and a0, a2, a0
+; RV32ZICOND-NEXT:    and a1, a2, a1
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: zero_singlebit2:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    slli a1, a1, 51
+; RV64ZICOND-NEXT:    srai a1, a1, 63
+; RV64ZICOND-NEXT:    and a0, a1, a0
+; RV64ZICOND-NEXT:    ret
+  %and = and i64 %rs2, 4096
+  %rc = icmp eq i64 %and, 0
+  %sel = select i1 %rc, i64 0, i64 %rs1
+  ret i64 %sel
+}
+
 define i64 @add1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: add1:
 ; RV32I:       # %bb.0:
@@ -779,21 +877,21 @@ define i64 @xor4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 define i64 @and1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: and1:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beqz a0, .LBB16_2
+; RV32I-NEXT:    beqz a0, .LBB18_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    and a2, a2, a4
 ; RV32I-NEXT:    and a1, a1, a3
-; RV32I-NEXT:  .LBB16_2:
+; RV32I-NEXT:  .LBB18_2:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: and1:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beqz a0, .LBB16_2
+; RV64I-NEXT:    beqz a0, .LBB18_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:  .LBB16_2:
+; RV64I-NEXT:  .LBB18_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -836,21 +934,21 @@ define i64 @and1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 define i64 @and2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: and2:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beqz a0, .LBB17_2
+; RV32I-NEXT:    beqz a0, .LBB19_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    and a4, a2, a4
 ; RV32I-NEXT:    and a3, a1, a3
-; RV32I-NEXT:  .LBB17_2:
+; RV32I-NEXT:  .LBB19_2:
 ; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    mv a1, a4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: and2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beqz a0, .LBB17_2
+; RV64I-NEXT:    beqz a0, .LBB19_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    and a2, a1, a2
-; RV64I-NEXT:  .LBB17_2:
+; RV64I-NEXT:  .LBB19_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -893,21 +991,21 @@ define i64 @and2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 define i64 @and3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: and3:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bnez a0, .LBB18_2
+; RV32I-NEXT:    bnez a0, .LBB20_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    and a2, a2, a4
 ; RV32I-NEXT:    and a1, a1, a3
-; RV32I-NEXT:  .LBB18_2:
+; RV32I-NEXT:  .LBB20_2:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: and3:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB18_2
+; RV64I-NEXT:    bnez a0, .LBB20_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:  .LBB18_2:
+; RV64I-NEXT:  .LBB20_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -950,21 +1048,21 @@ define i64 @and3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 define i64 @and4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: and4:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bnez a0, .LBB19_2
+; RV32I-NEXT:    bnez a0, .LBB21_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    and a4, a2, a4
 ; RV32I-NEXT:    and a3, a1, a3
-; RV32I-NEXT:  .LBB19_2:
+; RV32I-NEXT:  .LBB21_2:
 ; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    mv a1, a4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: and4:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB19_2
+; RV64I-NEXT:    bnez a0, .LBB21_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    and a2, a1, a2
-; RV64I-NEXT:  .LBB19_2:
+; RV64I-NEXT:  .LBB21_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1007,21 +1105,21 @@ define i64 @and4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: basic:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    bnez a0, .LBB20_2
+; RV32I-NEXT:    bnez a0, .LBB22_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    mv a2, a4
-; RV32I-NEXT:  .LBB20_2:
+; RV32I-NEXT:  .LBB22_2:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: basic:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB20_2
+; RV64I-NEXT:    bnez a0, .LBB22_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
-; RV64I-NEXT:  .LBB20_2:
+; RV64I-NEXT:  .LBB22_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -1067,19 +1165,19 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    or a2, a0, a1
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    mv a0, a4
-; RV32I-NEXT:    beqz a2, .LBB21_2
+; RV32I-NEXT:    beqz a2, .LBB23_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
-; RV32I-NEXT:  .LBB21_2:
+; RV32I-NEXT:  .LBB23_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: seteq:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beq a0, a1, .LBB21_2
+; RV64I-NEXT:    beq a0, a1, .LBB23_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB21_2:
+; RV64I-NEXT:  .LBB23_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1131,19 +1229,19 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    or a2, a0, a1
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    mv a0, a4
-; RV32I-NEXT:    bnez a2, .LBB22_2
+; RV32I-NEXT:    bnez a2, .LBB24_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
-; RV32I-NEXT:  .LBB22_2:
+; RV32I-NEXT:  .LBB24_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setne:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bne a0, a1, .LBB22_2
+; RV64I-NEXT:    bne a0, a1, .LBB24_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB22_2:
+; RV64I-NEXT:  .LBB24_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1190,28 +1288,28 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setgt:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB23_2
+; RV32I-NEXT:    beq a1, a3, .LBB25_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a0, a3, a1
-; RV32I-NEXT:    beqz a0, .LBB23_3
-; RV32I-NEXT:    j .LBB23_4
-; RV32I-NEXT:  .LBB23_2:
+; RV32I-NEXT:    beqz a0, .LBB25_3
+; RV32I-NEXT:    j .LBB25_4
+; RV32I-NEXT:  .LBB25_2:
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    bnez a0, .LBB23_4
-; RV32I-NEXT:  .LBB23_3:
+; RV32I-NEXT:    bnez a0, .LBB25_4
+; RV32I-NEXT:  .LBB25_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB23_4:
+; RV32I-NEXT:  .LBB25_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setgt:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    blt a1, a0, .LBB23_2
+; RV64I-NEXT:    blt a1, a0, .LBB25_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB23_2:
+; RV64I-NEXT:  .LBB25_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1261,28 +1359,28 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setge:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB24_2
+; RV32I-NEXT:    beq a1, a3, .LBB26_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a0, a1, a3
-; RV32I-NEXT:    bnez a0, .LBB24_3
-; RV32I-NEXT:    j .LBB24_4
-; RV32I-NEXT:  .LBB24_2:
+; RV32I-NEXT:    bnez a0, .LBB26_3
+; RV32I-NEXT:    j .LBB26_4
+; RV32I-NEXT:  .LBB26_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
-; RV32I-NEXT:    beqz a0, .LBB24_4
-; RV32I-NEXT:  .LBB24_3:
+; RV32I-NEXT:    beqz a0, .LBB26_4
+; RV32I-NEXT:  .LBB26_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB24_4:
+; RV32I-NEXT:  .LBB26_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setge:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bge a0, a1, .LBB24_2
+; RV64I-NEXT:    bge a0, a1, .LBB26_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB24_2:
+; RV64I-NEXT:  .LBB26_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1332,28 +1430,28 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setlt:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB25_2
+; RV32I-NEXT:    beq a1, a3, .LBB27_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a0, a1, a3
-; RV32I-NEXT:    beqz a0, .LBB25_3
-; RV32I-NEXT:    j .LBB25_4
-; RV32I-NEXT:  .LBB25_2:
+; RV32I-NEXT:    beqz a0, .LBB27_3
+; RV32I-NEXT:    j .LBB27_4
+; RV32I-NEXT:  .LBB27_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
-; RV32I-NEXT:    bnez a0, .LBB25_4
-; RV32I-NEXT:  .LBB25_3:
+; RV32I-NEXT:    bnez a0, .LBB27_4
+; RV32I-NEXT:  .LBB27_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB25_4:
+; RV32I-NEXT:  .LBB27_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setlt:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    blt a0, a1, .LBB25_2
+; RV64I-NEXT:    blt a0, a1, .LBB27_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB25_2:
+; RV64I-NEXT:  .LBB27_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1403,28 +1501,28 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setle:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB26_2
+; RV32I-NEXT:    beq a1, a3, .LBB28_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a0, a3, a1
-; RV32I-NEXT:    bnez a0, .LBB26_3
-; RV32I-NEXT:    j .LBB26_4
-; RV32I-NEXT:  .LBB26_2:
+; RV32I-NEXT:    bnez a0, .LBB28_3
+; RV32I-NEXT:    j .LBB28_4
+; RV32I-NEXT:  .LBB28_2:
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    beqz a0, .LBB26_4
-; RV32I-NEXT:  .LBB26_3:
+; RV32I-NEXT:    beqz a0, .LBB28_4
+; RV32I-NEXT:  .LBB28_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB26_4:
+; RV32I-NEXT:  .LBB28_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setle:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bge a1, a0, .LBB26_2
+; RV64I-NEXT:    bge a1, a0, .LBB28_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB26_2:
+; RV64I-NEXT:  .LBB28_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1474,28 +1572,28 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setugt:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB27_2
+; RV32I-NEXT:    beq a1, a3, .LBB29_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a3, a1
-; RV32I-NEXT:    beqz a0, .LBB27_3
-; RV32I-NEXT:    j .LBB27_4
-; RV32I-NEXT:  .LBB27_2:
+; RV32I-NEXT:    beqz a0, .LBB29_3
+; RV32I-NEXT:    j .LBB29_4
+; RV32I-NEXT:  .LBB29_2:
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    bnez a0, .LBB27_4
-; RV32I-NEXT:  .LBB27_3:
+; RV32I-NEXT:    bnez a0, .LBB29_4
+; RV32I-NEXT:  .LBB29_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB27_4:
+; RV32I-NEXT:  .LBB29_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setugt:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bltu a1, a0, .LBB27_2
+; RV64I-NEXT:    bltu a1, a0, .LBB29_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB27_2:
+; RV64I-NEXT:  .LBB29_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1545,28 +1643,28 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setuge:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB28_2
+; RV32I-NEXT:    beq a1, a3, .LBB30_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a1, a3
-; RV32I-NEXT:    bnez a0, .LBB28_3
-; RV32I-NEXT:    j .LBB28_4
-; RV32I-NEXT:  .LBB28_2:
+; RV32I-NEXT:    bnez a0, .LBB30_3
+; RV32I-NEXT:    j .LBB30_4
+; RV32I-NEXT:  .LBB30_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
-; RV32I-NEXT:    beqz a0, .LBB28_4
-; RV32I-NEXT:  .LBB28_3:
+; RV32I-NEXT:    beqz a0, .LBB30_4
+; RV32I-NEXT:  .LBB30_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB28_4:
+; RV32I-NEXT:  .LBB30_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setuge:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bgeu a0, a1, .LBB28_2
+; RV64I-NEXT:    bgeu a0, a1, .LBB30_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB28_2:
+; RV64I-NEXT:  .LBB30_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1616,28 +1714,28 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setult:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB29_2
+; RV32I-NEXT:    beq a1, a3, .LBB31_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a1, a3
-; RV32I-NEXT:    beqz a0, .LBB29_3
-; RV32I-NEXT:    j .LBB29_4
-; RV32I-NEXT:  .LBB29_2:
+; RV32I-NEXT:    beqz a0, .LBB31_3
+; RV32I-NEXT:    j .LBB31_4
+; RV32I-NEXT:  .LBB31_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
-; RV32I-NEXT:    bnez a0, .LBB29_4
-; RV32I-NEXT:  .LBB29_3:
+; RV32I-NEXT:    bnez a0, .LBB31_4
+; RV32I-NEXT:  .LBB31_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB29_4:
+; RV32I-NEXT:  .LBB31_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setult:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bltu a0, a1, .LBB29_2
+; RV64I-NEXT:    bltu a0, a1, .LBB31_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB29_2:
+; RV64I-NEXT:  .LBB31_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1687,28 +1785,28 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setule:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB30_2
+; RV32I-NEXT:    beq a1, a3, .LBB32_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a3, a1
-; RV32I-NEXT:    bnez a0, .LBB...
[truncated]

topperc
topperc reviewed Nov 28, 2023
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llvm/test/CodeGen/RISCV/condops.ll Outdated
@@ -3648,7 +3645,7 @@ define i64 @single_bit(i64 %x) {
;
; RV64XVENTANACONDOPS-LABEL: single_bit:
; RV64XVENTANACONDOPS: # %bb.0: # %entry
; RV64XVENTANACONDOPS-NEXT: andi a1, a0, 1024
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Isn't ANDI better, especially if we can use c.andi?

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Done.

topperc
topperc approved these changes Nov 29, 2023
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LGTM

@yetingk yetingk merged commit f73844d into llvm:main Nov 29, 2023
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@topperc topperc topperc approved these changes

@preames preames Awaiting requested review from preames

@lukel97 lukel97 Awaiting requested review from lukel97

@michaelmaitland michaelmaitland Awaiting requested review from michaelmaitland

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@yetingk @llvmbot @topperc