[Abandoned][AArch64] Assembly support for the Checked Pointer Arithmetic Extension #73776
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This introduces assembly support for the Checked Pointer Arithmetic Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture version. The changes include: * New subtarget feature for FEAT_CPA * New scalar instruction for pointer arithmetic * ADDPT, SUBPT, MADDPT, and MSUBPT * New SVE instructions for pointer arithmetic * ADDPT (vectors, predicated), ADDPT (vectors, unpredicated) * SUBPT (vectors, predicated), SUBPT (vectors, unpredicated) * MADPT and MLAPT * New ID_AA64ISAR3_EL1 system register Mode details about the extension can be found at: * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023 * https://developer.arm.com/documentation/ddi0602/2023-09/ Co-authored-by: Rodolfo Wottrich <rodolfo.wottrich@arm.com>
llvmbot
added
clang
|
@llvm/pr-subscribers-clang-driver @llvm/pr-subscribers-clang Author: Lucas Duarte Prates (pratlucas) ChangesPatch is 27.46 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73776.diff 19 Files Affected:
diff --git a/clang/test/Driver/aarch64-v95a.c b/clang/test/Driver/aarch64-v95a.c
index 6044a4f155db02c..366cade86a9fb71 100644
--- a/clang/test/Driver/aarch64-v95a.c
+++ b/clang/test/Driver/aarch64-v95a.c
@@ -13,3 +13,8 @@
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"
+// ===== Features supported on aarch64 =====
+
+// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
+// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
+// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+cpa"
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 38ccca56336abb9..90fd666da8d13b5 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -173,6 +173,7 @@ enum ArchExtKind : unsigned {
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
AEK_SMEFA64 = 71, // FEAT_SME_FA64
+ AEK_CPA = 72, // FEAT_CPA
AEK_NUM_EXTENSIONS
};
using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
@@ -295,6 +296,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+sme2,+fp8", 0},
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32", FEAT_INIT, "+sme2,+fp8", 0},
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT, "", 0},
+ {"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
// Special cases
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},
};
@@ -378,7 +380,8 @@ inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASv2}))};
-inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts)};
+inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
+ AArch64::ExtensionBitset({AArch64::AEK_CPA}))};
// For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
inline constexpr ArchInfo ARMV8R = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", (ARMV8_5A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_SSBS,
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 914ad0b68a624f6..4a829d3278fe0e9 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,9 @@ def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">;
+def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
+ "Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+
//===----------------------------------------------------------------------===//
// Architectures.
//
@@ -692,7 +695,7 @@ def HasV9_4aOps : SubtargetFeature<
def HasV9_5aOps : SubtargetFeature<
"v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions",
- [HasV9_4aOps]>;
+ [HasV9_4aOps, FeatureCPA]>;
def HasV8_0rOps : SubtargetFeature<
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e45..690ac0dcda62128 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -12446,6 +12446,58 @@ class SystemPXtI<bit L, string asm> :
BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs),
(ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XSeqPairClassOperand:$Rt)>;
+//----------------------------------------------------------------------------
+// 2023 Armv9.5 Extensions
+//----------------------------------------------------------------------------
+
+//---
+// Checked Pointer Arithmetic (FEAT_CPA)
+//---
+
+def LSLImm3ShiftOperand : AsmOperandClass {
+ let SuperClasses = [ExtendOperandLSL64];
+ let Name = "LSLImm3Shift";
+ let RenderMethod = "addLSLImm3ShifterOperands";
+ let DiagnosticType = "AddSubLSLImm3ShiftLarge";
+}
+
+def lsl_imm3_shift_operand : Operand<i32> {
+ let PrintMethod = "printShifter";
+ let ParserMatchClass = LSLImm3ShiftOperand;
+}
+
+// Base CPA scalar add/subtract with lsl #imm3 shift
+class BaseAddSubCPA<bit isSub, string asm> : I<(outs GPR64sp:$Rd),
+ (ins GPR64sp:$Rn, GPR64:$Rm, lsl_imm3_shift_operand:$shift_imm),
+ asm, "\t$Rd, $Rn, $Rm$shift_imm", "", []>, Sched<[]> {
+ bits<5> Rd;
+ bits<5> Rn;
+ bits<5> Rm;
+ bits<3> shift_imm;
+ let Inst{31} = 0b1;
+ let Inst{30} = isSub;
+ let Inst{29-21} = 0b011010000;
+ let Inst{20-16} = Rm;
+ let Inst{15-13} = 0b001;
+ let Inst{12-10} = shift_imm;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rd;
+}
+
+// Alias for CPA scalar add/subtract with no shift
+class AddSubCPAAlias<string asm, Instruction inst>
+ : InstAlias<asm#"\t$Rd, $Rn, $Rm",
+ (inst GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0)>;
+
+multiclass AddSubCPA<bit isSub, string asm> {
+ def _shift : BaseAddSubCPA<isSub, asm>;
+ def _noshift : AddSubCPAAlias<asm, !cast<Instruction>(NAME#"_shift")>;
+}
+
+class MulAccumCPA<bit isSub, string asm>
+ : BaseMulAccum<isSub, 0b011, GPR64, GPR64, asm, []>, Sched<[]> {
+ let Inst{31} = 0b1;
+}
//----------------------------------------------------------------------------
// Allow the size specifier tokens to be upper case, not just lower.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0a8abfae5051dd8..b94bc101dc6026d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -289,6 +289,8 @@ def HasCHK : Predicate<"Subtarget->hasCHK()">,
AssemblerPredicateWithAll<(all_of FeatureCHK), "chk">;
def HasGCS : Predicate<"Subtarget->hasGCS()">,
AssemblerPredicateWithAll<(all_of FeatureGCS), "gcs">;
+def HasCPA : Predicate<"Subtarget->hasCPA()">,
+ AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@@ -9367,6 +9369,10 @@ let Predicates = [HasD128] in {
}
}
+//===----------------------------===//
+// 2023 Architecture Extensions:
+//===----------------------------===//
+
let Predicates = [HasFP8] in {
defm F1CVTL : SIMDMixedTwoVectorFP8<0b00, "f1cvtl">;
defm F2CVTL : SIMDMixedTwoVectorFP8<0b01, "f2cvtl">;
@@ -9408,6 +9414,19 @@ let Predicates = [HasFP8DOT4] in {
defm FDOT : SIMDThreeSameVectorDOT4<"fdot">;
} // End let Predicates = [HasFP8DOT4]
+//===----------------------------------------------------------------------===//
+// Checked Pointer Arithmetic (FEAT_CPA)
+//===----------------------------------------------------------------------===//
+let Predicates = [HasCPA] in {
+ // Scalar add/subtract
+ defm ADDPT : AddSubCPA<0, "addpt">;
+ defm SUBPT : AddSubCPA<1, "subpt">;
+
+ // Scalar multiply-add/subtract
+ def MADDPT : MulAccumCPA<0, "maddpt">;
+ def MSUBPT : MulAccumCPA<1, "msubpt">;
+}
+
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 21cafe9b6c4453a..7587a07958a30c0 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -4163,3 +4163,24 @@ let Predicates = [HasSVE2orSME2, HasLUT] in {
// LUTI4 (two contiguous registers)
defm LUTI4_Z2ZZI : sve2_luti4_vector_vg2_index<"luti4">;
} // End HasSVE2orSME2, HasLUT
+
+//===----------------------------------------------------------------------===//
+// Checked Pointer Arithmetic (FEAT_CPA)
+//===----------------------------------------------------------------------===//
+let Predicates = [HasSVEorSME, HasCPA] in {
+ // Add/subtract (vectors, unpredicated)
+ def ADD_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b010, "addpt", ZPR64>;
+ def SUB_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b011, "subpt", ZPR64>;
+
+ // Add/subtract (vectors, predicated)
+ let DestructiveInstType = DestructiveBinaryComm in {
+ def ADD_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b100, "addpt", ZPR64>;
+ def SUB_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b101, "subpt", ZPR64>;
+ }
+
+ // Multiply-add vectors, writing multiplicand
+ def MAD_CPA : sve_int_mad_cpa<"madpt">;
+
+ // Multiply-add vectors, writing addend
+ def MLA_CPA : sve_int_mla_cpa<"mlapt">;
+}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index 65b97ff6956a11c..77ec445366ffc8a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -24,7 +24,7 @@ def A64FXModel : SchedMachineModel {
[HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2, HasSME2p1, HasSVE2p1,
HasSVE2p1_or_HasSME2p1, HasSMEF16F16, HasSSVE_FP8FMA, HasSMEF8F16, HasSMEF8F32,
- HasSMEFA64];
+ HasSMEFA64, HasCPA];
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index 503de3bee2b8678..53cf725f0e23575 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -19,7 +19,7 @@ def NeoverseN2Model : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- [HasSVE2p1]);
+ [HasSVE2p1, HasCPA]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 726be1a547b9519..75fbb85dce9d14a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -28,7 +28,7 @@ def NeoverseV1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCPA]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 3367d5d0cd315ff..658d7cdd23a63b2 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -22,7 +22,7 @@ def NeoverseV2Model : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- [HasSVE2p1]);
+ [HasSVE2p1, HasCPA]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index fbe1bf3c5238dbd..3f28d6deb0d3cde 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1541,6 +1541,13 @@ class AArch64Operand : public MCParsedAsmOperand {
getShiftExtendAmount() <= 4;
}
+ bool isLSLImm3Shift() const {
+ if (!isShiftExtend())
+ return false;
+ AArch64_AM::ShiftExtendType ET = getShiftExtendType();
+ return ET == AArch64_AM::LSL && getShiftExtendAmount() <= 7;
+ }
+
template<int Width> bool isMemXExtend() const {
if (!isExtend())
return false;
@@ -2091,6 +2098,12 @@ class AArch64Operand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createImm(Imm));
}
+ void addLSLImm3ShifterOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ unsigned Imm = getShiftExtendAmount();
+ Inst.addOperand(MCOperand::createImm(Imm));
+ }
+
void addSyspXzrPairOperand(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -3664,6 +3677,7 @@ static const struct Extension {
{"sme-f8f16", {AArch64::FeatureSMEF8F16}},
{"sme-f8f32", {AArch64::FeatureSMEF8F32}},
{"sme-fa64", {AArch64::FeatureSMEFA64}},
+ {"cpa", {AArch64::FeatureCPA}},
};
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
@@ -6064,6 +6078,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
"Invalid vector list, expected list with each SVE vector in the list "
"4 registers apart, and the first register in the range [z0, z3] or "
"[z16, z19] and with correct element type");
+ case Match_AddSubLSLImm3ShiftLarge:
+ return Error(Loc,
+ "expected 'lsl' with optional integer in range [0, 7]");
default:
llvm_unreachable("unexpected error code!");
}
@@ -6448,6 +6465,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidMemoryIndexed8:
case Match_InvalidMemoryIndexed16:
case Match_InvalidCondCode:
+ case Match_AddSubLSLImm3ShiftLarge:
case Match_AddSubRegExtendSmall:
case Match_AddSubRegExtendLarge:
case Match_AddSubSecondSource:
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index c0894e9c70680a4..cd2de130b3ce6d2 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -10424,3 +10424,34 @@ multiclass sve2_luti4_vector_vg2_index<string mnemonic> {
let Inst{23-22} = idx;
}
}
+
+//===----------------------------------------------------------------------===//
+// Checked Pointer Arithmetic (FEAT_CPA)
+//===----------------------------------------------------------------------===//
+class sve_int_mad_cpa<string asm>
+ : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Za),
+ asm, "\t$Zdn, $Zm, $Za", "", []>, Sched<[]> {
+ bits<5> Zdn;
+ bits<5> Zm;
+ bits<5> Za;
+ let Inst{31-24} = 0b01000100;
+ let Inst{23-22} = 0b11; // sz
+ let Inst{21} = 0b0;
+ let Inst{20-16} = Zm;
+ let Inst{15} = 0b1;
+ let Inst{14-10} = 0b10110; // opc
+ let Inst{9-5} = Za;
+ let Inst{4-0} = Zdn;
+
+ let Constraints = "$Zdn = $_Zdn";
+ let DestructiveInstType = DestructiveOther;
+ let ElementSize = ZPR64.ElementSize;
+ let hasSideEffects = 0;
+}
+
+class sve_int_mla_cpa<string asm>
+ : sve2_int_mla<0b11, 0b10100, asm, ZPR64, ZPR64> {
+ let Inst{15} = 0b1;
+
+ let ElementSize = ZPR64.ElementSize;
+}
diff --git a/llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s b/llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s
new file mode 100644
index 000000000000000..339f6a70ee07a2d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s
@@ -0,0 +1,69 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve -mattr=+cpa < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme -mattr=+cpa < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+cpa < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-SVESME
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-CPA
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-CPA
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
+// RUN: | llvm-objdump -d --mattr=+sve --mattr=+cpa - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
+// RUN: | llvm-objdump -d --mattr=+sve --mattr=-cpa - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
+// RUN: | llvm-objdump -d --mattr=-sve --mattr=+cpa - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+addpt z23.d, z13.d, z8.d
+// CHECK-INST: addpt z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x09,0xe8,0x04]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 04e809b7 <unknown>
+
+addpt z23.d, p3/m, z23.d, z13.d
+// CHECK-INST: addpt z23.d, p3/m, z23.d, z13.d
+// CHECK-ENCODING: [0xb7,0x0d,0xc4,0x04]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 04c40db7 <unknown>
+
+subpt z23.d, z13.d, z8.d
+// CHECK-INST: subpt z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x0d,0xe8,0x04]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 04e80db7 <unknown>
+
+subpt z23.d, p3/m, z23.d, z13.d
+// CHECK-INST: subpt z23.d, p3/m, z23.d, z13.d
+// CHECK-ENCODING: [0xb7,0x0d,0xc5,0x04]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 04c50db7 <unknown>
+
+madpt z0.d, z1.d, z31.d
+// CHECK-INST: madpt z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0xe0,0xdb,0xc1,0x44]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 44c1dbe0 <unknown>
+
+mlapt z0.d, z1.d, z31.d
+// CHECK-INST: mlapt z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd0,0xdf,0x44]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 44dfd020 <unknown>
diff --git a/llvm/test/MC/AArch64/armv9.5a-cpa.s b/llvm/test/MC/AArch64/armv9.5a-cpa.s
new file mode 100644
index 000000000000000..86932feeff8e41a
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.5a-cpa.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+cpa < %s | FileCheck %s
+// NORUN: not llvm-mc -triple aarch64 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-CPA %s
+
+addpt x0, x1, x2
+// CHECK: addpt x0, x1, x2 // encoding: [0x20,0x20,0x02,0x9a]
+// ERROR-NO-CPA: error: instruction requires: cpa
+
+addpt sp, sp, x2
+// CHECK: addpt sp, sp, x2 // encoding: [0xff,0x23,0x02,0x9a]
+// ERROR-NO-CPA: error: instruction requires: cpa
+
+addpt x0, x1, x2, lsl #0
+// CHECK: addpt x0, x1, x2 ...
[truncated]
|
|
@llvm/pr-subscribers-mc Author: Lucas Duarte Prates (pratlucas) ChangesPatch is 27.46 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73776.diff 19 Files Affected:
diff --git a/clang/test/Driver/aarch64-v95a.c b/clang/test/Driver/aarch64-v95a.c
index 6044a4f155db02c..366cade86a9fb71 100644
--- a/clang/test/Driver/aarch64-v95a.c
+++ b/clang/test/Driver/aarch64-v95a.c
@@ -13,3 +13,8 @@
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"
+// ===== Features supported on aarch64 =====
+
+// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
+// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
+// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+cpa"
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 38ccca56336abb9..90fd666da8d13b5 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -173,6 +173,7 @@ enum ArchExtKind : unsigned {
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
AEK_SMEFA64 = 71, // FEAT_SME_FA64
+ AEK_CPA = 72, // FEAT_CPA
AEK_NUM_EXTENSIONS
};
using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
@@ -295,6 +296,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+sme2,+fp8", 0},
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32", FEAT_INIT, "+sme2,+fp8", 0},
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT, "", 0},
+ {"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
// Special cases
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},
};
@@ -378,7 +380,8 @@ inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASv2}))};
-inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts)};
+inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
+ AArch64::ExtensionBitset({AArch64::AEK_CPA}))};
// For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
inline constexpr ArchInfo ARMV8R = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", (ARMV8_5A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_SSBS,
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 914ad0b68a624f6..4a829d3278fe0e9 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,9 @@ def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">;
+def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
+ "Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+
//===----------------------------------------------------------------------===//
// Architectures.
//
@@ -692,7 +695,7 @@ def HasV9_4aOps : SubtargetFeature<
def HasV9_5aOps : SubtargetFeature<
"v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions",
- [HasV9_4aOps]>;
+ [HasV9_4aOps, FeatureCPA]>;
def HasV8_0rOps : SubtargetFeature<
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e45..690ac0dcda62128 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -12446,6 +12446,58 @@ class SystemPXtI<bit L, string asm> :
BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs),
(ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XSeqPairClassOperand:$Rt)>;
+//----------------------------------------------------------------------------
+// 2023 Armv9.5 Extensions
+//----------------------------------------------------------------------------
+
+//---
+// Checked Pointer Arithmetic (FEAT_CPA)
+//---
+
+def LSLImm3ShiftOperand : AsmOperandClass {
+ let SuperClasses = [ExtendOperandLSL64];
+ let Name = "LSLImm3Shift";
+ let RenderMethod = "addLSLImm3ShifterOperands";
+ let DiagnosticType = "AddSubLSLImm3ShiftLarge";
+}
+
+def lsl_imm3_shift_operand : Operand<i32> {
+ let PrintMethod = "printShifter";
+ let ParserMatchClass = LSLImm3ShiftOperand;
+}
+
+// Base CPA scalar add/subtract with lsl #imm3 shift
+class BaseAddSubCPA<bit isSub, string asm> : I<(outs GPR64sp:$Rd),
+ (ins GPR64sp:$Rn, GPR64:$Rm, lsl_imm3_shift_operand:$shift_imm),
+ asm, "\t$Rd, $Rn, $Rm$shift_imm", "", []>, Sched<[]> {
+ bits<5> Rd;
+ bits<5> Rn;
+ bits<5> Rm;
+ bits<3> shift_imm;
+ let Inst{31} = 0b1;
+ let Inst{30} = isSub;
+ let Inst{29-21} = 0b011010000;
+ let Inst{20-16} = Rm;
+ let Inst{15-13} = 0b001;
+ let Inst{12-10} = shift_imm;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rd;
+}
+
+// Alias for CPA scalar add/subtract with no shift
+class AddSubCPAAlias<string asm, Instruction inst>
+ : InstAlias<asm#"\t$Rd, $Rn, $Rm",
+ (inst GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0)>;
+
+multiclass AddSubCPA<bit isSub, string asm> {
+ def _shift : BaseAddSubCPA<isSub, asm>;
+ def _noshift : AddSubCPAAlias<asm, !cast<Instruction>(NAME#"_shift")>;
+}
+
+class MulAccumCPA<bit isSub, string asm>
+ : BaseMulAccum<isSub, 0b011, GPR64, GPR64, asm, []>, Sched<[]> {
+ let Inst{31} = 0b1;
+}
//----------------------------------------------------------------------------
// Allow the size specifier tokens to be upper case, not just lower.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0a8abfae5051dd8..b94bc101dc6026d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -289,6 +289,8 @@ def HasCHK : Predicate<"Subtarget->hasCHK()">,
AssemblerPredicateWithAll<(all_of FeatureCHK), "chk">;
def HasGCS : Predicate<"Subtarget->hasGCS()">,
AssemblerPredicateWithAll<(all_of FeatureGCS), "gcs">;
+def HasCPA : Predicate<"Subtarget->hasCPA()">,
+ AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@@ -9367,6 +9369,10 @@ let Predicates = [HasD128] in {
}
}
+//===----------------------------===//
+// 2023 Architecture Extensions:
+//===----------------------------===//
+
let Predicates = [HasFP8] in {
defm F1CVTL : SIMDMixedTwoVectorFP8<0b00, "f1cvtl">;
defm F2CVTL : SIMDMixedTwoVectorFP8<0b01, "f2cvtl">;
@@ -9408,6 +9414,19 @@ let Predicates = [HasFP8DOT4] in {
defm FDOT : SIMDThreeSameVectorDOT4<"fdot">;
} // End let Predicates = [HasFP8DOT4]
+//===----------------------------------------------------------------------===//
+// Checked Pointer Arithmetic (FEAT_CPA)
+//===----------------------------------------------------------------------===//
+let Predicates = [HasCPA] in {
+ // Scalar add/subtract
+ defm ADDPT : AddSubCPA<0, "addpt">;
+ defm SUBPT : AddSubCPA<1, "subpt">;
+
+ // Scalar multiply-add/subtract
+ def MADDPT : MulAccumCPA<0, "maddpt">;
+ def MSUBPT : MulAccumCPA<1, "msubpt">;
+}
+
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 21cafe9b6c4453a..7587a07958a30c0 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -4163,3 +4163,24 @@ let Predicates = [HasSVE2orSME2, HasLUT] in {
// LUTI4 (two contiguous registers)
defm LUTI4_Z2ZZI : sve2_luti4_vector_vg2_index<"luti4">;
} // End HasSVE2orSME2, HasLUT
+
+//===----------------------------------------------------------------------===//
+// Checked Pointer Arithmetic (FEAT_CPA)
+//===----------------------------------------------------------------------===//
+let Predicates = [HasSVEorSME, HasCPA] in {
+ // Add/subtract (vectors, unpredicated)
+ def ADD_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b010, "addpt", ZPR64>;
+ def SUB_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b011, "subpt", ZPR64>;
+
+ // Add/subtract (vectors, predicated)
+ let DestructiveInstType = DestructiveBinaryComm in {
+ def ADD_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b100, "addpt", ZPR64>;
+ def SUB_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b101, "subpt", ZPR64>;
+ }
+
+ // Multiply-add vectors, writing multiplicand
+ def MAD_CPA : sve_int_mad_cpa<"madpt">;
+
+ // Multiply-add vectors, writing addend
+ def MLA_CPA : sve_int_mla_cpa<"mlapt">;
+}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index 65b97ff6956a11c..77ec445366ffc8a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -24,7 +24,7 @@ def A64FXModel : SchedMachineModel {
[HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2, HasSME2p1, HasSVE2p1,
HasSVE2p1_or_HasSME2p1, HasSMEF16F16, HasSSVE_FP8FMA, HasSMEF8F16, HasSMEF8F32,
- HasSMEFA64];
+ HasSMEFA64, HasCPA];
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index 503de3bee2b8678..53cf725f0e23575 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -19,7 +19,7 @@ def NeoverseN2Model : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- [HasSVE2p1]);
+ [HasSVE2p1, HasCPA]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 726be1a547b9519..75fbb85dce9d14a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -28,7 +28,7 @@ def NeoverseV1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCPA]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 3367d5d0cd315ff..658d7cdd23a63b2 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -22,7 +22,7 @@ def NeoverseV2Model : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- [HasSVE2p1]);
+ [HasSVE2p1, HasCPA]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index fbe1bf3c5238dbd..3f28d6deb0d3cde 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1541,6 +1541,13 @@ class AArch64Operand : public MCParsedAsmOperand {
getShiftExtendAmount() <= 4;
}
+ bool isLSLImm3Shift() const {
+ if (!isShiftExtend())
+ return false;
+ AArch64_AM::ShiftExtendType ET = getShiftExtendType();
+ return ET == AArch64_AM::LSL && getShiftExtendAmount() <= 7;
+ }
+
template<int Width> bool isMemXExtend() const {
if (!isExtend())
return false;
@@ -2091,6 +2098,12 @@ class AArch64Operand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createImm(Imm));
}
+ void addLSLImm3ShifterOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ unsigned Imm = getShiftExtendAmount();
+ Inst.addOperand(MCOperand::createImm(Imm));
+ }
+
void addSyspXzrPairOperand(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -3664,6 +3677,7 @@ static const struct Extension {
{"sme-f8f16", {AArch64::FeatureSMEF8F16}},
{"sme-f8f32", {AArch64::FeatureSMEF8F32}},
{"sme-fa64", {AArch64::FeatureSMEFA64}},
+ {"cpa", {AArch64::FeatureCPA}},
};
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
@@ -6064,6 +6078,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
"Invalid vector list, expected list with each SVE vector in the list "
"4 registers apart, and the first register in the range [z0, z3] or "
"[z16, z19] and with correct element type");
+ case Match_AddSubLSLImm3ShiftLarge:
+ return Error(Loc,
+ "expected 'lsl' with optional integer in range [0, 7]");
default:
llvm_unreachable("unexpected error code!");
}
@@ -6448,6 +6465,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidMemoryIndexed8:
case Match_InvalidMemoryIndexed16:
case Match_InvalidCondCode:
+ case Match_AddSubLSLImm3ShiftLarge:
case Match_AddSubRegExtendSmall:
case Match_AddSubRegExtendLarge:
case Match_AddSubSecondSource:
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index c0894e9c70680a4..cd2de130b3ce6d2 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -10424,3 +10424,34 @@ multiclass sve2_luti4_vector_vg2_index<string mnemonic> {
let Inst{23-22} = idx;
}
}
+
+//===----------------------------------------------------------------------===//
+// Checked Pointer Arithmetic (FEAT_CPA)
+//===----------------------------------------------------------------------===//
+class sve_int_mad_cpa<string asm>
+ : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Za),
+ asm, "\t$Zdn, $Zm, $Za", "", []>, Sched<[]> {
+ bits<5> Zdn;
+ bits<5> Zm;
+ bits<5> Za;
+ let Inst{31-24} = 0b01000100;
+ let Inst{23-22} = 0b11; // sz
+ let Inst{21} = 0b0;
+ let Inst{20-16} = Zm;
+ let Inst{15} = 0b1;
+ let Inst{14-10} = 0b10110; // opc
+ let Inst{9-5} = Za;
+ let Inst{4-0} = Zdn;
+
+ let Constraints = "$Zdn = $_Zdn";
+ let DestructiveInstType = DestructiveOther;
+ let ElementSize = ZPR64.ElementSize;
+ let hasSideEffects = 0;
+}
+
+class sve_int_mla_cpa<string asm>
+ : sve2_int_mla<0b11, 0b10100, asm, ZPR64, ZPR64> {
+ let Inst{15} = 0b1;
+
+ let ElementSize = ZPR64.ElementSize;
+}
diff --git a/llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s b/llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s
new file mode 100644
index 000000000000000..339f6a70ee07a2d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s
@@ -0,0 +1,69 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve -mattr=+cpa < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme -mattr=+cpa < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+cpa < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-SVESME
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-CPA
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-CPA
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
+// RUN: | llvm-objdump -d --mattr=+sve --mattr=+cpa - \
+// RUN: | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
+// RUN: | llvm-objdump -d --mattr=+sve --mattr=-cpa - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
+// RUN: | llvm-objdump -d --mattr=-sve --mattr=+cpa - \
+// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+addpt z23.d, z13.d, z8.d
+// CHECK-INST: addpt z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x09,0xe8,0x04]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 04e809b7 <unknown>
+
+addpt z23.d, p3/m, z23.d, z13.d
+// CHECK-INST: addpt z23.d, p3/m, z23.d, z13.d
+// CHECK-ENCODING: [0xb7,0x0d,0xc4,0x04]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 04c40db7 <unknown>
+
+subpt z23.d, z13.d, z8.d
+// CHECK-INST: subpt z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x0d,0xe8,0x04]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 04e80db7 <unknown>
+
+subpt z23.d, p3/m, z23.d, z13.d
+// CHECK-INST: subpt z23.d, p3/m, z23.d, z13.d
+// CHECK-ENCODING: [0xb7,0x0d,0xc5,0x04]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 04c50db7 <unknown>
+
+madpt z0.d, z1.d, z31.d
+// CHECK-INST: madpt z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0xe0,0xdb,0xc1,0x44]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 44c1dbe0 <unknown>
+
+mlapt z0.d, z1.d, z31.d
+// CHECK-INST: mlapt z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd0,0xdf,0x44]
+// CHECK-ERROR: instruction requires: cpa sve or sme
+// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
+// CHECK-ERROR-NO-CPA: instruction requires: cpa
+// CHECK-UNKNOWN: 44dfd020 <unknown>
diff --git a/llvm/test/MC/AArch64/armv9.5a-cpa.s b/llvm/test/MC/AArch64/armv9.5a-cpa.s
new file mode 100644
index 000000000000000..86932feeff8e41a
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.5a-cpa.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+cpa < %s | FileCheck %s
+// NORUN: not llvm-mc -triple aarch64 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-CPA %s
+
+addpt x0, x1, x2
+// CHECK: addpt x0, x1, x2 // encoding: [0x20,0x20,0x02,0x9a]
+// ERROR-NO-CPA: error: instruction requires: cpa
+
+addpt sp, sp, x2
+// CHECK: addpt sp, sp, x2 // encoding: [0xff,0x23,0x02,0x9a]
+// ERROR-NO-CPA: error: instruction requires: cpa
+
+addpt x0, x1, x2, lsl #0
+// CHECK: addpt x0, x1, x2 ...
[truncated]
|
You can test this locally with the following command:git-clang-format --diff 511218642bc5df7815423de211192dd577eb3a9c bff5119a857124f113d9dc499701ad87941fe1c3 -- clang/test/Driver/aarch64-v95a.c llvm/include/llvm/TargetParser/AArch64TargetParser.h llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp llvm/unittests/TargetParser/TargetParserTest.cppView the diff from clang-format here.diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 90fd666da8..7d946dab57 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -422,9 +422,9 @@ inline constexpr CpuInfo CpuInfos[] = {
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
{"cortex-a55", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_RCPC}))},
{"cortex-a510", ARMV9A,
(AArch64::ExtensionBitset(
{AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SB,
@@ -440,13 +440,13 @@ inline constexpr CpuInfo CpuInfos[] = {
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
{"cortex-a65", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
- AArch64::AEK_FP16, AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
{"cortex-a65ae", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
- AArch64::AEK_FP16, AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
{"cortex-a72", ARMV8A,
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
@@ -454,38 +454,38 @@ inline constexpr CpuInfo CpuInfos[] = {
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
{"cortex-a75", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_RCPC}))},
{"cortex-a76", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
{"cortex-a76ae", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
{"cortex-a77", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_SSBS}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_RCPC,
+ AArch64::AEK_DOTPROD, AArch64::AEK_SSBS}))},
{"cortex-a78", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PROFILE}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS,
+ AArch64::AEK_PROFILE}))},
{"cortex-a78c", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PROFILE, AArch64::AEK_FLAGM, AArch64::AEK_PAUTH,
- AArch64::AEK_FP16FML}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS,
+ AArch64::AEK_PROFILE, AArch64::AEK_FLAGM,
+ AArch64::AEK_PAUTH, AArch64::AEK_FP16FML}))},
{"cortex-a710", ARMV9A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_MTE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
- AArch64::AEK_SB, AArch64::AEK_I8MM, AArch64::AEK_FP16FML,
- AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_BF16}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_MTE, AArch64::AEK_PAUTH,
+ AArch64::AEK_FLAGM, AArch64::AEK_SB,
+ AArch64::AEK_I8MM, AArch64::AEK_FP16FML,
+ AArch64::AEK_SVE, AArch64::AEK_SVE2,
+ AArch64::AEK_SVE2BITPERM, AArch64::AEK_BF16}))},
{"cortex-a715", ARMV9A,
(AArch64::ExtensionBitset(
{AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE,
@@ -494,23 +494,22 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::AEK_PROFILE, AArch64::AEK_SVE, AArch64::AEK_SVE2BITPERM,
AArch64::AEK_BF16, AArch64::AEK_FLAGM}))},
{"cortex-a720", ARMV9_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE,
- AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
- AArch64::AEK_PROFILE}))},
- {"cortex-r82", ARMV8R,
- (AArch64::ExtensionBitset({AArch64::AEK_LSE}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS,
+ AArch64::AEK_MTE, AArch64::AEK_FP16FML,
+ AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
+ AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
+ AArch64::AEK_PREDRES, AArch64::AEK_PROFILE}))},
+ {"cortex-r82", ARMV8R, (AArch64::ExtensionBitset({AArch64::AEK_LSE}))},
{"cortex-x1", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PROFILE}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS,
+ AArch64::AEK_PROFILE}))},
{"cortex-x1c", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PAUTH, AArch64::AEK_PROFILE}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS,
+ AArch64::AEK_PAUTH, AArch64::AEK_PROFILE}))},
{"cortex-x2", ARMV9A,
(AArch64::ExtensionBitset(
{AArch64::AEK_MTE, AArch64::AEK_BF16, AArch64::AEK_I8MM,
@@ -525,20 +524,20 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PREDRES,
AArch64::AEK_FLAGM, AArch64::AEK_SSBS}))},
{"cortex-x4", ARMV9_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE,
- AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
- AArch64::AEK_PROFILE}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS,
+ AArch64::AEK_MTE, AArch64::AEK_FP16FML,
+ AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
+ AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
+ AArch64::AEK_PREDRES, AArch64::AEK_PROFILE}))},
{"neoverse-e1", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
- AArch64::AEK_FP16, AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
+ AArch64::AEK_RCPC, AArch64::AEK_SSBS}))},
{"neoverse-n1", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
- AArch64::AEK_FP16, AArch64::AEK_PROFILE, AArch64::AEK_RCPC,
- AArch64::AEK_SSBS}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
+ AArch64::AEK_PROFILE, AArch64::AEK_RCPC,
+ AArch64::AEK_SSBS}))},
{"neoverse-n2", ARMV8_5A,
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
@@ -580,8 +579,7 @@ inline constexpr CpuInfo CpuInfos[] = {
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE}))},
{"apple-a10", ARMV8A,
(AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_CRC,
- AArch64::AEK_RDM}))},
+ AArch64::AEK_CRC, AArch64::AEK_RDM}))},
{"apple-a11", ARMV8_2A,
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16}))},
@@ -589,32 +587,32 @@ inline constexpr CpuInfo CpuInfos[] = {
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16}))},
{"apple-a13", ARMV8_4A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_SHA3, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML}))},
{"apple-a14", ARMV8_5A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_SHA3, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML}))},
{"apple-a15", ARMV8_5A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML,
- AArch64::AEK_BF16, AArch64::AEK_I8MM}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_SHA3, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML, AArch64::AEK_BF16,
+ AArch64::AEK_I8MM}))},
{"apple-a16", ARMV8_5A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML,
- AArch64::AEK_BF16, AArch64::AEK_I8MM}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_SHA3, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML, AArch64::AEK_BF16,
+ AArch64::AEK_I8MM}))},
{"apple-m1", ARMV8_5A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_SHA3, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML}))},
{"apple-m2", ARMV8_5A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML,
- AArch64::AEK_BF16, AArch64::AEK_I8MM}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_SHA3, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML, AArch64::AEK_BF16,
+ AArch64::AEK_I8MM}))},
{"apple-s4", ARMV8_3A,
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16}))},
@@ -626,16 +624,13 @@ inline constexpr CpuInfo CpuInfos[] = {
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
{"exynos-m4", ARMV8_2A,
(AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD,
- AArch64::AEK_FP16}))},
+ AArch64::AEK_DOTPROD, AArch64::AEK_FP16}))},
{"exynos-m5", ARMV8_2A,
(AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD,
- AArch64::AEK_FP16}))},
+ AArch64::AEK_DOTPROD, AArch64::AEK_FP16}))},
{"falkor", ARMV8A,
(AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_CRC,
- AArch64::AEK_RDM}))},
+ AArch64::AEK_CRC, AArch64::AEK_RDM}))},
{"saphira", ARMV8_3A,
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_PROFILE}))},
@@ -643,11 +638,9 @@ inline constexpr CpuInfo CpuInfos[] = {
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
{"thunderx2t99", ARMV8_1A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2}))},
{"thunderx3t110", ARMV8_3A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2}))},
{"thunderx", ARMV8A,
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
@@ -661,21 +654,20 @@ inline constexpr CpuInfo CpuInfos[] = {
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
{"tsv110", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
+ AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML, AArch64::AEK_PROFILE}))},
{"a64fx", ARMV8_2A,
(AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16,
- AArch64::AEK_SVE}))},
+ AArch64::AEK_FP16, AArch64::AEK_SVE}))},
{"carmel", ARMV8_2A,
(AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16}))},
{"ampere1", ARMV8_6A,
(AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_SB, AArch64::AEK_SSBS,
- AArch64::AEK_RAND}))},
+ AArch64::AEK_SHA3, AArch64::AEK_FP16,
+ AArch64::AEK_SB, AArch64::AEK_SSBS,
+ AArch64::AEK_RAND}))},
{"ampere1a", ARMV8_6A,
(AArch64::ExtensionBitset(
{AArch64::AEK_FP16, AArch64::AEK_RAND, AArch64::AEK_SM4,
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 3f28d6deb0..8875657a4a 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3676,7 +3676,7 @@ static const struct Extension {
{"sme-lutv2", {AArch64::FeatureSME_LUTv2}},
{"sme-f8f16", {AArch64::FeatureSMEF8F16}},
{"sme-f8f32", {AArch64::FeatureSMEF8F32}},
- {"sme-fa64", {AArch64::FeatureSMEFA64}},
+ {"sme-fa64", {AArch64::FeatureSMEFA64}},
{"cpa", {AArch64::FeatureCPA}},
};
@@ -6079,8 +6079,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
"4 registers apart, and the first register in the range [z0, z3] or "
"[z16, z19] and with correct element type");
case Match_AddSubLSLImm3ShiftLarge:
- return Error(Loc,
- "expected 'lsl' with optional integer in range [0, 7]");
+ return Error(Loc, "expected 'lsl' with optional integer in range [0, 7]");
default:
llvm_unreachable("unexpected error code!");
}
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index dab90fa221..9b847e7e47 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1061,21 +1061,21 @@ INSTANTIATE_TEST_SUITE_P(
::testing::Values(
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
@@ -1099,48 +1099,53 @@ INSTANTIATE_TEST_SUITE_P(
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a520", "armv9.2-a", "crypto-neon-fp-armv8",
(AArch64::ExtensionBitset(
- {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE,
- AArch64::AEK_SVE2, AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_SIMD,
- AArch64::AEK_RCPC, AArch64::AEK_RAS, AArch64::AEK_CRC,
- AArch64::AEK_FP, AArch64::AEK_SB, AArch64::AEK_SSBS,
- AArch64::AEK_MTE, AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
- AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
- AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})),
+ {AArch64::AEK_BF16, AArch64::AEK_I8MM,
+ AArch64::AEK_SVE, AArch64::AEK_SVE2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_LSE, AArch64::AEK_RDM,
+ AArch64::AEK_SIMD, AArch64::AEK_RCPC,
+ AArch64::AEK_RAS, AArch64::AEK_CRC,
+ AArch64::AEK_FP, AArch64::AEK_SB,
+ AArch64::AEK_SSBS, AArch64::AEK_MTE,
+ AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
+ AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
+ AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})),
"9.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a65", "armv8.2-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16,
- AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RCPC,
- AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
+ AArch64::AEK_FP, AArch64::AEK_FP16,
+ AArch64::AEK_LSE, AArch64::AEK_RAS,
+ AArch64::AEK_RCPC, AArch64::AEK_RDM,
+ AArch64::AEK_SIMD, AArch64::AEK_SSBS})),
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a65ae", "armv8.2-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16,
- AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RCPC,
- AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
+ AArch64::AEK_FP, AArch64::AEK_FP16,
+ AArch64::AEK_LSE, AArch64::AEK_RAS,
+ AArch64::AEK_RCPC, AArch64::AEK_RDM,
+ AArch64::AEK_SIMD, AArch64::AEK_SSBS})),
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
@@ -1223,14 +1228,17 @@ INSTANTIATE_TEST_SUITE_P(
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-a720", "armv9.2-a", "crypto-neon-fp-armv8",
(AArch64::ExtensionBitset(
- {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE,
- AArch64::AEK_SVE2, AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_SIMD,
- AArch64::AEK_RCPC, AArch64::AEK_RAS, AArch64::AEK_CRC,
- AArch64::AEK_FP, AArch64::AEK_SB, AArch64::AEK_SSBS,
- AArch64::AEK_MTE, AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
- AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
- AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
+ {AArch64::AEK_BF16, AArch64::AEK_I8MM,
+ AArch64::AEK_SVE, AArch64::AEK_SVE2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_LSE, AArch64::AEK_RDM,
+ AArch64::AEK_SIMD, AArch64::AEK_RCPC,
+ AArch64::AEK_RAS, AArch64::AEK_CRC,
+ AArch64::AEK_FP, AArch64::AEK_SB,
+ AArch64::AEK_SSBS, AArch64::AEK_MTE,
+ AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
+ AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
+ AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
AArch64::AEK_PROFILE})),
"9.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
@@ -1261,11 +1269,12 @@ INSTANTIATE_TEST_SUITE_P(
"9-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_RDM, AArch64::AEK_SSBS,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_SIMD,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_RAS,
- AArch64::AEK_RCPC, AArch64::AEK_LSE, AArch64::AEK_SB})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_RDM,
+ AArch64::AEK_SSBS, AArch64::AEK_DOTPROD,
+ AArch64::AEK_FP, AArch64::AEK_SIMD,
+ AArch64::AEK_FP16, AArch64::AEK_FP16FML,
+ AArch64::AEK_RAS, AArch64::AEK_RCPC,
+ AArch64::AEK_LSE, AArch64::AEK_SB})),
"8-R"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8",
@@ -1315,45 +1324,48 @@ INSTANTIATE_TEST_SUITE_P(
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-x4", "armv9.2-a", "crypto-neon-fp-armv8",
(AArch64::ExtensionBitset(
- {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SVE,
- AArch64::AEK_SVE2, AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_SIMD,
- AArch64::AEK_RCPC, AArch64::AEK_RAS, AArch64::AEK_CRC,
- AArch64::AEK_FP, AArch64::AEK_SB, AArch64::AEK_SSBS,
- AArch64::AEK_MTE, AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
- AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
- AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
+ {AArch64::AEK_BF16, AArch64::AEK_I8MM,
+ AArch64::AEK_SVE, AArch64::AEK_SVE2,
+ AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
+ AArch64::AEK_LSE, AArch64::AEK_RDM,
+ AArch64::AEK_SIMD, AArch64::AEK_RCPC,
+ AArch64::AEK_RAS, AArch64::AEK_CRC,
+ AArch64::AEK_FP, AArch64::AEK_SB,
+ AArch64::AEK_SSBS, AArch64::AEK_MTE,
+ AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
+ AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
+ AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
AArch64::AEK_PROFILE})),
"9.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cyclone", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_NONE, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a7", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_NONE, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a8", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_NONE, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a9", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_NONE, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a10", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_RDM, AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a11", "armv8.2-a", "crypto-neon-fp-armv8",
@@ -1364,11 +1376,11 @@ INSTANTIATE_TEST_SUITE_P(
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a12", "armv8.3-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE,
- AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC,
- AArch64::AEK_FP16})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD, AArch64::AEK_LSE,
+ AArch64::AEK_RAS, AArch64::AEK_RDM,
+ AArch64::AEK_RCPC, AArch64::AEK_FP16})),
"8.3-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a13", "armv8.4-a", "crypto-neon-fp-armv8",
@@ -1429,70 +1441,71 @@ INSTANTIATE_TEST_SUITE_P(
"8.5-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-s4", "armv8.3-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE,
- AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC,
- AArch64::AEK_FP16})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD, AArch64::AEK_LSE,
+ AArch64::AEK_RAS, AArch64::AEK_RDM,
+ AArch64::AEK_RCPC, AArch64::AEK_FP16})),
"8.3-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-s5", "armv8.3-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE,
- AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC,
- AArch64::AEK_FP16})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD, AArch64::AEK_LSE,
+ AArch64::AEK_RAS, AArch64::AEK_RDM,
+ AArch64::AEK_RCPC, AArch64::AEK_FP16})),
"8.3-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"exynos-m4", "armv8.2-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16,
- AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
- AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
+ AArch64::AEK_FP, AArch64::AEK_FP16,
+ AArch64::AEK_LSE, AArch64::AEK_RAS,
+ AArch64::AEK_RDM, AArch64::AEK_SIMD})),
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"exynos-m5", "armv8.2-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16,
- AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
- AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
+ AArch64::AEK_FP, AArch64::AEK_FP16,
+ AArch64::AEK_LSE, AArch64::AEK_RAS,
+ AArch64::AEK_RDM, AArch64::AEK_SIMD})),
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"falkor", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_RDM})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD, AArch64::AEK_RDM})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"kryo", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"neoverse-e1", "armv8.2-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16,
- AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RCPC,
- AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
+ AArch64::AEK_FP, AArch64::AEK_FP16,
+ AArch64::AEK_LSE, AArch64::AEK_RAS,
+ AArch64::AEK_RCPC, AArch64::AEK_RDM,
+ AArch64::AEK_SIMD, AArch64::AEK_SSBS})),
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
(AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16,
- AArch64::AEK_LSE, AArch64::AEK_PROFILE, AArch64::AEK_RAS,
- AArch64::AEK_RCPC, AArch64::AEK_RDM, AArch64::AEK_SIMD,
- AArch64::AEK_SSBS})),
+ {AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_DOTPROD, AArch64::AEK_FP,
+ AArch64::AEK_FP16, AArch64::AEK_LSE, AArch64::AEK_PROFILE,
+ AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_RDM,
+ AArch64::AEK_SIMD, AArch64::AEK_SSBS})),
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"neoverse-n2", "armv8.5-a", "crypto-neon-fp-armv8",
@@ -1544,10 +1557,10 @@ INSTANTIATE_TEST_SUITE_P(
"8.4-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_FP,
- AArch64::AEK_SIMD})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_LSE,
+ AArch64::AEK_RDM, AArch64::AEK_FP,
+ AArch64::AEK_SIMD})),
"8.1-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"thunderx3t110", "armv8.3-a", "crypto-neon-fp-armv8",
@@ -1558,27 +1571,27 @@ INSTANTIATE_TEST_SUITE_P(
"8.3-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"thunderx", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SIMD, AArch64::AEK_FP})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_SIMD,
+ AArch64::AEK_FP})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"thunderxt81", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SIMD, AArch64::AEK_FP})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_SIMD,
+ AArch64::AEK_FP})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"thunderxt83", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SIMD, AArch64::AEK_FP})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_SIMD,
+ AArch64::AEK_FP})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"thunderxt88", "armv8-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SIMD, AArch64::AEK_FP})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_SIMD,
+ AArch64::AEK_FP})),
"8-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"tsv110", "armv8.2-a", "crypto-neon-fp-armv8",
@@ -1591,11 +1604,11 @@ INSTANTIATE_TEST_SUITE_P(
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"a64fx", "armv8.2-a", "crypto-neon-fp-armv8",
- (AArch64::ExtensionBitset(
- {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_FP16,
- AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_SVE,
- AArch64::AEK_RDM})),
+ (AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
+ AArch64::AEK_SHA2, AArch64::AEK_FP,
+ AArch64::AEK_SIMD, AArch64::AEK_FP16,
+ AArch64::AEK_RAS, AArch64::AEK_LSE,
+ AArch64::AEK_SVE, AArch64::AEK_RDM})),
"8.2-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"carmel", "armv8.2-a", "crypto-neon-fp-armv8",
|
pratlucas
changed the title
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