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[Mips] Optimize (shift x (and y, BitWidth - 1)) to (shift x, y) #73889

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merged 1 commit into from
Dec 29, 2023

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yingopq
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@yingopq yingopq commented Nov 30, 2023

Do optimization to turn x >> (shift & 31/63) into a single srlv instead of andi + srlv, since the mips variable shift instruction already implicitly masks the shift, like x86, wasm and AMDGPU. Copy the X86DAGToDAGISel::isUnneededShiftMask() function to MIPS for checking whether need combine two instructions to one.

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github-actions bot commented Nov 30, 2023

✅ With the latest revision this PR passed the C/C++ code formatter.

@yingopq yingopq changed the title Optimize (shift x (and y, BitWidth - 1)) to (shift x, y) [Mips] Optimize (shift x (and y, BitWidth - 1)) to (shift x, y) Nov 30, 2023

const APInt &RHS = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
if (RHS.countr_one() >= ShAmtBits) {
LLVM_DEBUG(dbgs() << DEBUG_TYPE << " Need optimize 'and & shl/srl/sra' and operand value bits is " << RHS.countr_one() << "\n");
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80 columns

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Thanks!

Do optimization to turn x >> (shift & 31/63) into a single srlv
instead of andi + srlv, since the mips variable shift instruction
already implicitly masks the shift, like x86, wasm and AMDGPU.
Copy the X86DAGToDAGISel::isUnneededShiftMask() function to MIPS
for checking whether need combine two instructions to one.
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yingopq commented Dec 12, 2023

Hi @topperc,
Could you help review this patch?
Thanks.

@brad0 brad0 requested a review from topperc December 24, 2023 07:45
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LGTM

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yingopq commented Dec 29, 2023

LGTM

@topperc Thanks, I did not know I can @who to help commit this patch?

@xgupta xgupta merged commit e13e95b into llvm:main Dec 29, 2023
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yingopq commented Dec 29, 2023

@xgupta Thanks!

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3 participants