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[RISCV] Rework IDiv and FDiv pipes on SiFive7 #73970
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@llvm/pr-subscribers-backend-risc-v Author: Michael Maitland (michaelmaitland) ChangesSet BufferSize=0 and remove Super pipes for these resources. Full diff: https://github.com/llvm/llvm-project/pull/73970.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 53ef9d1baf7b59a..261c22ea35317e2 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -213,12 +213,12 @@ let SchedModel = SiFive7Model in {
let BufferSize = 0 in {
def SiFive7PipeA : ProcResource<1>;
def SiFive7PipeB : ProcResource<1>;
+def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
+def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
def SiFive7PipeV : ProcResource<1>;
}
let BufferSize = 1 in {
-def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
-def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
def SiFive7VA : ProcResource<1> { let Super = SiFive7PipeV; } // Arithmetic sequencer
def SiFive7VL : ProcResource<1> { let Super = SiFive7PipeV; } // Load sequencer
def SiFive7VS : ProcResource<1> { let Super = SiFive7PipeV; } // Store sequencer
|
@@ -213,12 +213,12 @@ let SchedModel = SiFive7Model in { | |||
let BufferSize = 0 in { | |||
def SiFive7PipeA : ProcResource<1>; | |||
def SiFive7PipeB : ProcResource<1>; | |||
def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division |
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I don't know why these need a Super class. Their usages already say SiFive7PipeB in the ResourceCycles explicitly.
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IIUC, the bahavior is different. If there is no Super
, SiFive7PipeB
will be released after 1 cycle; if Super
is specified, SiFive7PipeB
will still be occupied after 1 cycle as SiFive7IDiv implictly use it. I don't know the details about the real pipeline, is it desired?
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I didn't mean to keep the Super class. As @wangpc-pp points out that the description of the PR says it is removed. I will push a fixup.
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The PR description says Super
is removed but we still have it?
@@ -213,12 +213,12 @@ let SchedModel = SiFive7Model in { | |||
let BufferSize = 0 in { | |||
def SiFive7PipeA : ProcResource<1>; | |||
def SiFive7PipeB : ProcResource<1>; | |||
def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division |
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IIUC, the bahavior is different. If there is no Super
, SiFive7PipeB
will be released after 1 cycle; if Super
is specified, SiFive7PipeB
will still be occupied after 1 cycle as SiFive7IDiv implictly use it. I don't know the details about the real pipeline, is it desired?
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LGTM.
(Is this not covered by some llvm-mca tests?)
Set BufferSize=0 and remove Super pipes for these resources.
I just added a test case. Check out the commit that adds it to see the diff (I precomitted the test) |
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Set BufferSize=0 and remove Super pipes for these resources.