Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[GlobalISel] Improve combines for extend operation by taking hint ins… #74125

Merged
merged 1 commit into from
Jan 17, 2024

Conversation

dfszabo
Copy link
Contributor

@dfszabo dfszabo commented Dec 1, 2023

…tructions into account

Hint instructions like G_ASSERT_ZEXT cann be viewed as a copy. Including this fact into the combiner allows the match more patterns involving such instructions.

@llvmbot
Copy link
Collaborator

llvmbot commented Dec 1, 2023

@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-llvm-globalisel

Author: Dávid Ferenc Szabó (dfszabo)

Changes

…tructions into account

Hint instructions like G_ASSERT_ZEXT cann be viewed as a copy. Including this fact into the combiner allows the match more patterns involving such instructions.


Full diff: https://github.com/llvm/llvm-project/pull/74125.diff

2 Files Affected:

  • (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+6)
  • (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir (+186-40)
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index c2a7c2d01188129..069752807f3904d 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2280,6 +2280,9 @@ bool CombinerHelper::matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) {
   assert(MI.getOpcode() == TargetOpcode::G_ANYEXT && "Expected a G_ANYEXT");
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
+  Register OriginalSrcReg = getSrcRegIgnoringCopies(SrcReg, MRI);
+  if (OriginalSrcReg.isValid())
+    SrcReg = OriginalSrcReg;
   LLT DstTy = MRI.getType(DstReg);
   return mi_match(SrcReg, MRI,
                   m_GTrunc(m_all_of(m_Reg(Reg), m_SpecificType(DstTy))));
@@ -2306,6 +2309,9 @@ bool CombinerHelper::matchCombineExtOfExt(
           MI.getOpcode() == TargetOpcode::G_ZEXT) &&
          "Expected a G_[ASZ]EXT");
   Register SrcReg = MI.getOperand(1).getReg();
+  Register OriginalSrcReg = getSrcRegIgnoringCopies(SrcReg, MRI);
+  if (OriginalSrcReg.isValid())
+    SrcReg = OriginalSrcReg;
   MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
   // Match exts with the same opcode, anyext([sz]ext) and sext(zext).
   unsigned Opc = MI.getOpcode();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
index 1b8ba9f7bec1d3a..a431a6764d06f7b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
@@ -6,21 +6,41 @@ body:             |
   bb.1:
   liveins: $x0
     ; CHECK-LABEL: name: test_combine_anyext_trunc
-    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
-    ; CHECK: $x1 = COPY [[COPY]](s64)
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+    ; CHECK-NEXT: $x1 = COPY [[COPY]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s32) = G_TRUNC %0(s64)
     %2:_(s64) = G_ANYEXT %1(s32)
     $x1 = COPY %2(s64)
 ...
 ---
+name:            test_combine_anyext_trunc_with_hint
+body:             |
+  bb.1:
+  liveins: $x0
+    ; CHECK-LABEL: name: test_combine_anyext_trunc_with_hint
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+    ; CHECK-NEXT: $x1 = COPY [[COPY]](s64)
+    %0:_(s64) = COPY $x0
+    %1:_(s32) = G_TRUNC %0(s64)
+    %2:_(s32) = G_ASSERT_ZEXT %1(s32), 11
+    %3:_(s64) = G_ANYEXT %2(s32)
+    $x1 = COPY %3(s64)
+...
+---
 name:            test_combine_anyext_trunc_vec
 body:             |
   bb.1:
   liveins: $q0
     ; CHECK-LABEL: name: test_combine_anyext_trunc_vec
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
-    ; CHECK: $q0 = COPY [[COPY]](<2 x s64>)
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+    ; CHECK-NEXT: $q0 = COPY [[COPY]](<2 x s64>)
     %0:_(<2 x s64>) = COPY $q0
     %1:_(<2 x s32>) = G_TRUNC %0(<2 x s64>)
     %2:_(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
@@ -32,23 +52,44 @@ body:             |
   bb.1:
   liveins: $h0
     ; CHECK-LABEL: name: test_combine_anyext_anyext
-    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
-    ; CHECK: $x0 = COPY [[ANYEXT]](s64)
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
     %0:_(s16) = COPY $h0
     %1:_(s32) = G_ANYEXT %0(s16)
     %2:_(s64) = G_ANYEXT %1(s32)
     $x0 = COPY %2(s64)
 ...
 ---
+name:            test_combine_anyext_anyext_with_hint
+body:             |
+  bb.1:
+  liveins: $h0
+    ; CHECK-LABEL: name: test_combine_anyext_anyext_with_hint
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
+    %0:_(s16) = COPY $h0
+    %1:_(s32) = G_ANYEXT %0(s16)
+    %2:_(s32) = G_ASSERT_ZEXT %1(s32), 11
+    %3:_(s64) = G_ANYEXT %2(s32)
+    $x0 = COPY %3(s64)
+...
+---
 name:            test_combine_anyext_anyext_vec
 body:             |
   bb.1:
   liveins: $s0
     ; CHECK-LABEL: name: test_combine_anyext_anyext_vec
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s16>)
-    ; CHECK: $q0 = COPY [[ANYEXT]](<2 x s64>)
+    ; CHECK: liveins: $s0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<2 x s64>)
     %0:_(<2 x s16>) = COPY $s0
     %1:_(<2 x s32>) = G_ANYEXT %0(<2 x s16>)
     %2:_(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
@@ -60,23 +101,44 @@ body:             |
   bb.1:
   liveins: $h0
     ; CHECK-LABEL: name: test_combine_anyext_sext
-    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
-    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
-    ; CHECK: $x0 = COPY [[SEXT]](s64)
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[SEXT]](s64)
     %0:_(s16) = COPY $h0
     %1:_(s32) = G_SEXT %0(s16)
     %2:_(s64) = G_ANYEXT %1(s32)
     $x0 = COPY %2(s64)
 ...
 ---
+name:            test_combine_anyext_sext_with_hint
+body:             |
+  bb.1:
+  liveins: $h0
+    ; CHECK-LABEL: name: test_combine_anyext_sext_with_hint
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[SEXT]](s64)
+    %0:_(s16) = COPY $h0
+    %1:_(s32) = G_SEXT %0(s16)
+    %2:_(s32) = G_ASSERT_ZEXT %1(s32), 11
+    %3:_(s64) = G_ANYEXT %2(s32)
+    $x0 = COPY %3(s64)
+...
+---
 name:            test_combine_anyext_sext_vec
 body:             |
   bb.1:
   liveins: $s0
     ; CHECK-LABEL: name: test_combine_anyext_sext_vec
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
-    ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s16>)
-    ; CHECK: $q0 = COPY [[SEXT]](<2 x s64>)
+    ; CHECK: liveins: $s0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: $q0 = COPY [[SEXT]](<2 x s64>)
     %0:_(<2 x s16>) = COPY $s0
     %1:_(<2 x s32>) = G_SEXT %0(<2 x s16>)
     %2:_(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
@@ -88,23 +150,44 @@ body:             |
   bb.1:
   liveins: $h0
     ; CHECK-LABEL: name: test_combine_anyext_zext
-    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
-    ; CHECK: $x0 = COPY [[ZEXT]](s64)
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
     %0:_(s16) = COPY $h0
     %1:_(s32) = G_ZEXT %0(s16)
     %2:_(s64) = G_ANYEXT %1(s32)
     $x0 = COPY %2(s64)
 ...
 ---
+name:            test_combine_anyext_zext_with_hint
+body:             |
+  bb.1:
+  liveins: $h0
+    ; CHECK-LABEL: name: test_combine_anyext_zext_with_hint
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+    %0:_(s16) = COPY $h0
+    %1:_(s32) = G_ZEXT %0(s16)
+    %2:_(s32) = G_ASSERT_ZEXT %1(s32), 11
+    %3:_(s64) = G_ANYEXT %2(s32)
+    $x0 = COPY %3(s64)
+...
+---
 name:            test_combine_anyext_zext_vec
 body:             |
   bb.1:
   liveins: $s0
     ; CHECK-LABEL: name: test_combine_anyext_zext_vec
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s16>)
-    ; CHECK: $q0 = COPY [[ZEXT]](<2 x s64>)
+    ; CHECK: liveins: $s0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
     %0:_(<2 x s16>) = COPY $s0
     %1:_(<2 x s32>) = G_ZEXT %0(<2 x s16>)
     %2:_(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
@@ -116,23 +199,44 @@ body:             |
   bb.1:
   liveins: $h0
     ; CHECK-LABEL: name: test_combine_sext_sext
-    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
-    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
-    ; CHECK: $x0 = COPY [[SEXT]](s64)
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[SEXT]](s64)
     %0:_(s16) = COPY $h0
     %1:_(s32) = G_SEXT %0(s16)
     %2:_(s64) = G_SEXT %1(s32)
     $x0 = COPY %2(s64)
 ...
 ---
+name:            test_combine_sext_sext_with_hint
+body:             |
+  bb.1:
+  liveins: $h0
+    ; CHECK-LABEL: name: test_combine_sext_sext_with_hint
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[SEXT]](s64)
+    %0:_(s16) = COPY $h0
+    %1:_(s32) = G_SEXT %0(s16)
+    %2:_(s32) = G_ASSERT_SEXT %1(s32), 11
+    %3:_(s64) = G_SEXT %2(s32)
+    $x0 = COPY %3(s64)
+...
+---
 name:            test_combine_sext_sext_vec
 body:             |
   bb.1:
   liveins: $s0
     ; CHECK-LABEL: name: test_combine_sext_sext_vec
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
-    ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s16>)
-    ; CHECK: $q0 = COPY [[SEXT]](<2 x s64>)
+    ; CHECK: liveins: $s0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: $q0 = COPY [[SEXT]](<2 x s64>)
     %0:_(<2 x s16>) = COPY $s0
     %1:_(<2 x s32>) = G_SEXT %0(<2 x s16>)
     %2:_(<2 x s64>) = G_SEXT %1(<2 x s32>)
@@ -144,23 +248,44 @@ body:             |
   bb.1:
   liveins: $h0
     ; CHECK-LABEL: name: test_combine_sext_zext
-    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
-    ; CHECK: $x0 = COPY [[ZEXT]](s64)
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
     %0:_(s16) = COPY $h0
     %1:_(s32) = G_ZEXT %0(s16)
     %2:_(s64) = G_SEXT %1(s32)
     $x0 = COPY %2(s64)
 ...
 ---
+name:            test_combine_sext_zext_with_hint
+body:             |
+  bb.1:
+  liveins: $h0
+    ; CHECK-LABEL: name: test_combine_sext_zext_with_hint
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+    %0:_(s16) = COPY $h0
+    %1:_(s32) = G_ZEXT %0(s16)
+    %2:_(s32) = G_ASSERT_ZEXT %1(s32), 11
+    %3:_(s64) = G_SEXT %2(s32)
+    $x0 = COPY %3(s64)
+...
+---
 name:            test_combine_sext_zext_vec
 body:             |
   bb.1:
   liveins: $s0
     ; CHECK-LABEL: name: test_combine_sext_zext_vec
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s16>)
-    ; CHECK: $q0 = COPY [[ZEXT]](<2 x s64>)
+    ; CHECK: liveins: $s0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
     %0:_(<2 x s16>) = COPY $s0
     %1:_(<2 x s32>) = G_ZEXT %0(<2 x s16>)
     %2:_(<2 x s64>) = G_SEXT %1(<2 x s32>)
@@ -172,23 +297,44 @@ body:             |
   bb.1:
   liveins: $h0
     ; CHECK-LABEL: name: test_combine_zext_zext
-    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
-    ; CHECK: $x0 = COPY [[ZEXT]](s64)
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
     %0:_(s16) = COPY $h0
     %1:_(s32) = G_ZEXT %0(s16)
     %2:_(s64) = G_ZEXT %1(s32)
     $x0 = COPY %2(s64)
 ...
 ---
+name:            test_combine_zext_zext_with_hint
+body:             |
+  bb.1:
+  liveins: $h0
+    ; CHECK-LABEL: name: test_combine_zext_zext_with_hint
+    ; CHECK: liveins: $h0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
+    ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+    %0:_(s16) = COPY $h0
+    %1:_(s32) = G_ZEXT %0(s16)
+    %2:_(s32) = G_ASSERT_ZEXT %1(s32), 11
+    %3:_(s64) = G_ZEXT %2(s32)
+    $x0 = COPY %3(s64)
+...
+---
 name:            test_combine_zext_zext_vec
 body:             |
   bb.1:
   liveins: $s0
     ; CHECK-LABEL: name: test_combine_zext_zext_vec
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s16>)
-    ; CHECK: $q0 = COPY [[ZEXT]](<2 x s64>)
+    ; CHECK: liveins: $s0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
     %0:_(<2 x s16>) = COPY $s0
     %1:_(<2 x s32>) = G_ZEXT %0(<2 x s16>)
     %2:_(<2 x s64>) = G_ZEXT %1(<2 x s32>)

@dfszabo dfszabo force-pushed the main-global-isel-anyext-trunc-combine branch from e9063a2 to 035d210 Compare December 1, 2023 19:29
@dfszabo
Copy link
Contributor Author

dfszabo commented Jan 8, 2024

Greetings @arsenm @aemerson, if you have time can you review this?

Copy link
Contributor

@arsenm arsenm left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

lgtm with nit

@@ -6,21 +6,41 @@ body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_combine_anyext_trunc
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can you pre-commit the change from CHECK to CHECK-NEXT?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Done.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Splitting it into 2 commits in the same PR is pointless, as the merge behavior is squash and submit. You can directly push the regen to main

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ohh apologies I didn't knew this squash behavior, I am used to bitbucket. I don't have rights to push directly to main, should I create a PR with the update test?

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yes

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Okay, created one: #77756

@dfszabo dfszabo force-pushed the main-global-isel-anyext-trunc-combine branch from 035d210 to 1aa46d5 Compare January 9, 2024 12:14
…tructions into account

Hint instructions like G_ASSERT_ZEXT can be viewed as a copy. Including this fact into the combiner allows to match more patterns involving such instructions.
@dfszabo dfszabo force-pushed the main-global-isel-anyext-trunc-combine branch from 1aa46d5 to a419b6b Compare January 12, 2024 18:00
@arsenm arsenm merged commit 55172b7 into llvm:main Jan 17, 2024
4 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

3 participants