[PowerPC][CodeGen] Exploit STMW and LMW in 32-bit big-endian mode. #74415
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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| // Record the first reg that STMW/LMW are going to merge since STMW/LMW save | ||
| // from rN to r31. | ||
| MergeFrom = CSI[BeginI].getReg(); |
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This is unnecessary complicating. LMW/STMW only applies for AIX 32-bit. For AIX, we just need to find the first GPR(assume the CSI is sorted on ascending ordering), that would be the MergeFrom. On AIX, CSRs always contain the lowest GPR till R31.
| ; CHECK-NEXT: mtlr 0 | ||
| ; CHECK-NEXT: bl | ||
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| @a = external local_unnamed_addr global i32, align 4 |
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case is too complicated. Please use below one
define dso_local void @test_simple() #0 {
entry:
call void asm sideeffect "nop", "~{r16}"()
ret void
}
| static cl::opt<bool> | ||
| EnableLoadStoreMultiple("ppc-enable-load-store-multiple", | ||
| cl::desc("Enable load/store multiple (only " | ||
| "support in 32-bit big-endian mode)."), |
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Instead of 32-bit big-endian, maybe it is better to limit this under AIX-32 bit.
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| @@ -2399,6 +2405,43 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots( | |||
| return AllSpilledToReg; | |||
| } | |||
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| static void findContinuousLoadStore(const MachineFunction *MF, | |||
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| static void findContinuousLoadStore(const MachineFunction *MF, | |
| static bool findConsecutiveLoadStore(const MachineFunction *MF, |
Return true if consecutive ld/std found.
| ArrayRef<CalleeSavedInfo> CSI, | ||
| Register &MergeFrom) { | ||
| const MachineFrameInfo &MFI = MF->getFrameInfo(); | ||
| int64_t Offset = MFI.estimateStackSize(*MF); |
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Could we use PPCFrameLowering::determineFrameLayout() to determine the stack size on PPC?
This patch exploits the stmw and lmw instructions. Max to r13~r31 continuous store/load instructions can be merged to stmw/lmw, which saves code size.