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[AMDGPU] Flip the default value of maybeAtomic. NFCI. #75220

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merged 2 commits into from
Jan 9, 2024
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[AMDGPU] Flip the default value of maybeAtomic. NFCI. #75220

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429d0a2
[AMDGPU] Flip the default value of maybeAtomic. NFCI.
jayfoad Dec 12, 2023
c5b7d3b
Merge remote-tracking branch 'origin/main' into maybeatomic-default
jayfoad Jan 9, 2024
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4 changes: 0 additions & 4 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -477,7 +477,6 @@ class MUBUF_Load_Pseudo <string opName,
let has_vdata = !not(!or(isLds, isLdsOpc));
let mayLoad = 1;
let mayStore = isLds;
let maybeAtomic = 1;
let Uses = !if(!or(isLds, isLdsOpc) , [EXEC, M0], [EXEC]);
let tfe = isTFE;
let lds = isLds;
Expand Down Expand Up @@ -567,7 +566,6 @@ class MUBUF_Store_Pseudo <string opName,
getAddrName<addrKindCopy>.ret;
let mayLoad = 0;
let mayStore = 1;
let maybeAtomic = 1;
let elements = getMUBUFElements<store_vt>.ret;
let tfe = isTFE;
}
Expand Down Expand Up @@ -618,7 +616,6 @@ class MUBUF_Pseudo_Store_Lds<string opName>
let LGKM_CNT = 1;
let mayLoad = 1;
let mayStore = 1;
let maybeAtomic = 1;

let has_vdata = 0;
let has_vaddr = 0;
Expand Down Expand Up @@ -680,7 +677,6 @@ class MUBUF_Atomic_Pseudo<string opName,
let has_glc = 0;
let has_dlc = 0;
let has_sccb = 1;
let maybeAtomic = 1;
let AsmMatchConverter = "cvtMubufAtomic";
}

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1 change: 0 additions & 1 deletion llvm/lib/Target/AMDGPU/DSInstructions.td
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Expand Up @@ -19,7 +19,6 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
// Most instruction load and store data, so set this as the default.
let mayLoad = 1;
let mayStore = 1;
let maybeAtomic = 1;

let hasSideEffects = 0;
let SchedRW = [WriteLDS];
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/EXPInstructions.td
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Expand Up @@ -20,6 +20,7 @@ class EXPCommon<bit row, bit done, string asm = ""> : InstSI<
let EXP_CNT = 1;
let mayLoad = done;
let mayStore = 1;
let maybeAtomic = 0;
let UseNamedOperandTable = 1;
let Uses = !if(row, [EXEC, M0], [EXEC]);
let SchedRW = [WriteExport];
Expand Down
7 changes: 0 additions & 7 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
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Expand Up @@ -173,7 +173,6 @@ class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
let has_saddr = HasSaddr;
let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
let maybeAtomic = 1;

let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
Expand All @@ -195,7 +194,6 @@ class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
let has_saddr = HasSaddr;
let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
let maybeAtomic = 1;
}

multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
Expand All @@ -221,7 +219,6 @@ class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
let has_vaddr = 0;
let has_saddr = 1;
let enabled_saddr = EnableSaddr;
let maybeAtomic = 1;
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");

let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
Expand Down Expand Up @@ -288,7 +285,6 @@ class FLAT_Global_Store_AddTid_Pseudo <string opName, RegisterClass vdataClass,
let has_vaddr = 0;
let has_saddr = 1;
let enabled_saddr = EnableSaddr;
let maybeAtomic = 1;
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
}

Expand Down Expand Up @@ -331,7 +327,6 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
let has_sve = EnableSVE;
let sve = EnableVaddr;
let PseudoInstr = opName#!if(EnableSVE, "_SVS", !if(EnableSaddr, "_SADDR", !if(EnableVaddr, "", "_ST")));
let maybeAtomic = 1;

let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
Expand Down Expand Up @@ -360,7 +355,6 @@ class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit En
let has_sve = EnableSVE;
let sve = EnableVaddr;
let PseudoInstr = opName#!if(EnableSVE, "_SVS", !if(EnableSaddr, "_SADDR", !if(EnableVaddr, "", "_ST")));
let maybeAtomic = 1;
}

multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedOutput = 0> {
Expand Down Expand Up @@ -450,7 +444,6 @@ class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins,
let has_vdst = 0;
let has_sccb = 1;
let sccbValue = 0;
let maybeAtomic = 1;
let IsAtomicNoRet = 1;
}

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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/LDSDIRInstructions.td
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Expand Up @@ -48,6 +48,7 @@ class LDSDIR_Common<string opName, string asm = "", bit direct> : InstSI<
let hasSideEffects = 0;
let mayLoad = 1;
let mayStore = 0;
let maybeAtomic = 0;

string Mnemonic = opName;
let UseNamedOperandTable = 1;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIInstrFormats.td
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Expand Up @@ -91,7 +91,7 @@ class InstSI <dag outs, dag ins, string asm = "",
field bit VOP3_OPSEL = 0;

// Is it possible for this instruction to be atomic?
field bit maybeAtomic = 0;
field bit maybeAtomic = 1;

// This bit indicates that this is a VI instruction which is renamed
// in GFX9. Required for correct mapping from pseudo to MC.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIInstructions.td
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Expand Up @@ -111,7 +111,6 @@ def ATOMIC_FENCE : SPseudoInstSI<
[(atomic_fence (i32 timm:$ordering), (i32 timm:$scope))],
"ATOMIC_FENCE $ordering, $scope"> {
let hasSideEffects = 1;
let maybeAtomic = 1;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
Expand Down Expand Up @@ -557,6 +556,7 @@ def SI_MASKED_UNREACHABLE : SPseudoInstSI <(outs), (ins),
let hasNoSchedulingInfo = 1;
let FixedSize = 1;
let isMeta = 1;
let maybeAtomic = 0;
}

// Used as an isel pseudo to directly emit initialization with an
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SMInstructions.td
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Expand Up @@ -29,6 +29,7 @@ class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
let mayStore = 0;
let mayLoad = 1;
let hasSideEffects = 0;
let maybeAtomic = 0;
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This preserves the existing behaviour but it feels wrong. In practice it means that SIMemoryLegalizer does not set glc on volatile SMEM loads.

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Probably should fix this in a separate change

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#77443

let UseNamedOperandTable = 1;
let SchedRW = [WriteSMEM];

Expand Down