[RISCV Add some vsetvli insertion test cases with vmv.s.x+reduction. NFC

[topperc]

These test cases where intended to get a single vsetvli by using the vmv.s.x intrinsic with the same LMUL as the reduction. This works for FP, but does not work for integer.

I believe #71501 will break this for FP too. Hopefully the vsetvli pass can be taught to fix this.

[preames]

LGTM

For the record, the difference between integer and float is very weird here.

[preames]

For the record, the difference between integer and float is very weird here.

Congrats, you nerd sniped me. :)

I dug into this, and it turns out to be a difference caused by the LMUL1 subreg stuff (which we apparently only do for int?), and a gap in the backwards walk code.

A draft patch follows. (Sorry for the huge inline comment, attaching files appears broken today?) Note that the fixme inline needs addressed before this can become a real patch, and there's definitely some style cleanup needed.

diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index b2d36b362b3a..6fe82991c82f 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1472,6 +1472,14 @@ static bool isNonZeroAVL(const MachineOperand &MO,
   return 0 != MO.getImm();
 }
 
+static bool hasSameAVL(const MachineOperand &AVL1, const MachineOperand &AVL2) {
+  if (AVL1.isReg() && AVL2.isReg())
+    return AVL1.getReg() == AVL2.getReg();
+  if (AVL1.isImm() && AVL2.isImm())
+    return AVL1.getImm() == AVL2.getImm();
+  return false;
+}
+
 // Return true if we can mutate PrevMI to match MI without changing any the
 // fields which would be observed.
 static bool canMutatePriorConfig(const MachineInstr &PrevMI,
@@ -1490,15 +1498,24 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI,
     if (Used.VLZeroness) {
       if (isVLPreservingConfig(PrevMI))
         return false;
-      if (!isNonZeroAVL(MI.getOperand(1), MRI) ||
-          !isNonZeroAVL(PrevMI.getOperand(1), MRI))
-        return false;
+      if (!hasSameAVL(MI.getOperand(1), PrevMI.getOperand(1)))
+        if (!isNonZeroAVL(MI.getOperand(1), MRI) ||
+            !isNonZeroAVL(PrevMI.getOperand(1), MRI))
+          return false;
     }
 
     // TODO: Track whether the register is defined between
     // PrevMI and MI.
-    if (MI.getOperand(1).isReg() &&
-        RISCV::X0 != MI.getOperand(1).getReg())
+    auto regMayBeDefinedBetween = [&]() {
+      auto &AVL1 = PrevMI.getOperand(1);
+      auto &AVL2 = MI.getOperand(1);
+      // FIXME: This strongly assumes SSA. Rewrite using MRI interface.
+      if (AVL1.isReg() && AVL2.isReg() && AVL1.getReg() == AVL2.getReg())
+        return false;
+      return RISCV::X0 != AVL2.getReg();
+    };
+
+    if (MI.getOperand(1).isReg() && regMayBeDefinedBetween())
       return false;
   }
 
@@ -1519,7 +1536,6 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) {
   Used.demandVTYPE();
   SmallVector<MachineInstr*> ToDelete;
   for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
-
     if (!isVectorConfigInstr(MI)) {
       doUnion(Used, getDemanded(MI, MRI, ST));
       continue;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
index 6ebbc37f4afd..b652804813e4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
@@ -63,9 +63,8 @@ define <32 x i32> @insertelt_v32i32_31(<32 x i32> %a, i32 %y) {
 ; CHECK-LABEL: insertelt_v32i32_31:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT:    vmv.s.x v16, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT:    vmv.s.x v16, a0
 ; CHECK-NEXT:    vslideup.vi v8, v16, 31
 ; CHECK-NEXT:    ret
   %b = insertelement <32 x i32> %a, i32 %y, i32 31
@@ -101,9 +100,8 @@ define <64 x i32> @insertelt_v64i32_63(<64 x i32> %a, i32 %y) {
 ; CHECK-LABEL: insertelt_v64i32_63:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT:    vmv.s.x v24, a0
 ; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT:    vmv.s.x v24, a0
 ; CHECK-NEXT:    vslideup.vi v16, v24, 31
 ; CHECK-NEXT:    ret
   %b = insertelement <64 x i32> %a, i32 %y, i32 63