[Hexagon] Flip subreg bit for reverse pairs hvx .new

[quic-akaryaki]

In .new instructions, the upper vector of a reverse pair (e.g. V4 in V4:5) should be referenced with an odd sss value.

[llvmbot]

@llvm/pr-subscribers-mc

Author: None (quic-akaryaki)

Changes

In .new instructions, the upper vector of a reverse pair (e.g. V4 in V4:5) should be referenced with an odd sss value.

---

Full diff: https://github.com/llvm/llvm-project/pull/75873.diff

3 Files Affected:

• (modified) llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (+2)
• (modified) llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (+4-2)
• (added) llvm/test/MC/Hexagon/hvx-nv-pair-reverse.s (+18)

diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index c7e22d7d308b04..44a5cd73c6e89f 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -512,6 +512,8 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
         const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
         const unsigned ProdPairIndex =
             Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
+        if (Rev)
+          SubregBit = !SubregBit;
         Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
       } else if (SubregBit)
         // Hexagon PRM 10.11 New-value operands
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
index 9cf004cf4c9a5e..a6de2ab9c75a26 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
@@ -1036,8 +1036,10 @@ unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
                                             unsigned Producer2) {
   // If we're a single vector consumer of a double producer, set subreg bit
   // based on if we're accessing the lower or upper register component
-  if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer))
-    return (Consumer - Hexagon::V0) & 0x1;
+  if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
+    unsigned Rev = IsReverseVecRegPair(Producer);
+    return ((Consumer - Hexagon::V0) & 0x1) ^ Rev;
+  }
   if (Producer2 != Hexagon::NoRegister)
     return Consumer == Producer;
   return 0;
diff --git a/llvm/test/MC/Hexagon/hvx-nv-pair-reverse.s b/llvm/test/MC/Hexagon/hvx-nv-pair-reverse.s
new file mode 100644
index 00000000000000..fea353af1fd06e
--- /dev/null
+++ b/llvm/test/MC/Hexagon/hvx-nv-pair-reverse.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc -arch=hexagon -mv69 -mhvx -filetype=obj %s | \
+# RUN:   llvm-objdump --arch=hexagon --mcpu=hexagonv69 --mattr=+hvx -d - | \
+# RUN:   FileCheck %s
+# CHECK: 00000000 <.text>:
+
+{
+  V4:5.w = vadd(V1:0.w, V3:2.w)
+  vmem(r0+#0) = v4.new
+}
+# CHECK-NEXT: 1c6240c5 { 	v4:5.w = vadd(v1:0.w,v3:2.w)
+# CHECK-NEXT: 2820c023   	vmem(r0+#0x0) = v4.new }
+
+{
+  V4:5.w = vadd(V1:0.w, V3:2.w)
+  vmem(r0+#0) = v5.new
+}
+# CHECK-NEXT: 1c6240c5 { 	v4:5.w = vadd(v1:0.w,v3:2.w)
+# CHECK-NEXT: 2820c022   	vmem(r0+#0x0) = v5.new }

[SundeepKushwaha]

LGTM

[androm3da]

instead of arch=hexagon I think you want triple=hexagon as seems to be the trend in other tests.