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[FastISel][AArch64] Compare Instruction Miscompilation Fix #75993

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merged 7 commits into from
Jan 3, 2024
Merged

[FastISel][AArch64] Compare Instruction Miscompilation Fix #75993

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5657561
[FastISel][AArch64] compare instruction miscompilation fix
brendaso1 Dec 19, 2023
cdc10d8
Simplify test/CodeGen/AArch64/fastisel-shift-and-cmp.ll
brendaso1 Dec 25, 2023
9652999
removed extraneous function in unit test
brendaso1 Dec 25, 2023
44d4231
clean up unit test
brendaso1 Dec 26, 2023
a495c27
Removed left shift and compare merging logic because that cannot be r…
brendaso1 Jan 1, 2024
4457315
moved unit test to arm64-fast-isel-icmp.ll
brendaso1 Jan 2, 2024
7017aec
removed unnecessary changes to selectBranch
brendaso1 Jan 2, 2024
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9 changes: 0 additions & 9 deletions llvm/lib/Target/AArch64/AArch64FastISel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1231,15 +1231,6 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
// Only extend the RHS within the instruction if there is a valid extend type.
if (ExtendType != AArch64_AM::InvalidShiftExtend && RHS->hasOneUse() &&
isValueAvailable(RHS)) {
if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4)) {
Register RHSReg = getRegForValue(SI->getOperand(0));
if (!RHSReg)
return 0;
return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType,
C->getZExtValue(), SetFlags, WantResult);
}
Register RHSReg = getRegForValue(RHS);
if (!RHSReg)
return 0;
Expand Down
16 changes: 16 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
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Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function icmp_i8_shift_and_cmp --version 4
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s

define i32 @icmp_eq_imm(i32 %a) nounwind ssp {
Expand Down Expand Up @@ -257,3 +258,18 @@ entry:
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}

define i32 @icmp_i8_shift_and_cmp(i8 %a, i8 %b) {
entry:
; CHECK-LABEL: icmp_i8_shift_and_cmp:
; CHECK: ubfiz [[REG1:w[0-9]+]], w0, #3, #5
; CHECK-NEXT: sxtb [[REG0:w[0-9]+]], w1
; CHECK-NEXT: cmp [[REG0]], [[REG1]], sxtb
; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
; CHECK-NEXT: and w0, [[REG]], #0x1
%op = shl i8 %a, 3
%cmp = icmp eq i8 %b, %op
%conv = zext i1 %cmp to i32
ret i32 %conv
}