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[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. #76061
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@llvm/pr-subscribers-backend-risc-v Author: Yeting Kuo (yetingk) ChangesThe spimm operand is an immediate whose only 4-5th bits could be setted. Full diff: https://github.com/llvm/llvm-project/pull/76061.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53e2b6b4d94ea0..5c4dbb2249a116 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -462,10 +462,10 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
return MCDisassembler::Success;
}
-// spimm is based on rlist now.
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
uint64_t Address, const void *Decoder) {
- // TODO: check if spimm matches rlist
+ if (!isShiftedUInt<2, 4>(Imm))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index a78f3624446871..2b3f08bc4a1a4f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -70,7 +70,7 @@ def spimm : Operand<OtherVT> {
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
- return isShiftedUInt<5, 4>(Imm);
+ return isShiftedUInt<2, 4>(Imm);
}];
}
|
Ping. |
Is this testable? |
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, | ||
uint64_t Address, const void *Decoder) { | ||
// TODO: check if spimm matches rlist | ||
if (!isShiftedUInt<2, 4>(Imm)) |
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I don't this check can ever fail. The caller looks like
tmp = fieldFromInstruction(insn, 2, 2) << 4;
if (!Check(S, decodeZcmpSpimm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
So its guaranteed to be a isShiftedUInt<2, 4>
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Removed this check. Sorry I didn't survey enough code about this.
The spimm operand is an immediate whose only 4-5th bit could be setted and not based on rlist operand.
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LGTM
The spimm operand is an immediate that only its 4-5th bits could be setted.