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[X86] Remove RAO-INT from Grandridge #76420
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According to latest spec: https://cdrdv2.intel.com/v1/dl/getContent/671368
llvmbot
added
clang
Clang issues not falling into any other category
backend:X86
labels
Dec 27, 2023
@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-clang Author: Freddy Ye (FreddyLeaf) ChangesAccording to latest spec: https://cdrdv2.intel.com/v1/dl/getContent/671368 Full diff: https://github.com/llvm/llvm-project/pull/76420.diff 3 Files Affected:
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index 1ae6faea776785..27c7b4a271fee8 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -2515,7 +2515,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32,CHECK_GRR_M32
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32
// RUN: %clang -march=arrowlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
@@ -2572,7 +2572,6 @@
// CHECK_SRF_M32: #define __PRFCHW__ 1
// CHECK_SRF_M32: #define __PTWRITE__ 1
// CHECK_SRF_M32-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M32: #define __RAOINT__ 1
// CHECK_SRF_M32: #define __RDPID__ 1
// CHECK_SRF_M32: #define __RDRND__ 1
// CHECK_SRF_M32: #define __RDSEED__ 1
@@ -2618,7 +2617,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64,CHECK_GRR_M64
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64
// RUN: %clang -march=arrowlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
@@ -2675,7 +2674,6 @@
// CHECK_SRF_M64: #define __PRFCHW__ 1
// CHECK_SRF_M64: #define __PTWRITE__ 1
// CHECK_SRF_M64-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M64: #define __RAOINT__ 1
// CHECK_SRF_M64: #define __RDPID__ 1
// CHECK_SRF_M64: #define __RDRND__ 1
// CHECK_SRF_M64: #define __RDSEED__ 1
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 5fd6828f43129d..e89ddcc570c96c 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1256,11 +1256,6 @@ def ProcessorFeatures {
list<SubtargetFeature> SRFFeatures =
!listconcat(ADLFeatures, SRFAdditionalFeatures);
- // Grandridge
- list<SubtargetFeature> GRRAdditionalFeatures = [FeatureRAOINT];
- list<SubtargetFeature> GRRFeatures =
- !listconcat(SRFFeatures, GRRAdditionalFeatures);
-
// Arrowlake S
list<SubtargetFeature> ARLSAdditionalFeatures = [FeatureAVXVNNIINT16,
FeatureSHA512,
@@ -1706,10 +1701,10 @@ foreach P = ["goldmont_plus", "goldmont-plus"] in {
}
def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
ProcessorFeatures.TRMTuning>;
-def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
- ProcessorFeatures.TRMTuning>;
-def : ProcModel<"grandridge", AlderlakePModel, ProcessorFeatures.GRRFeatures,
+foreach P = ["sierraforest", "grandridge"] in {
+ def : ProcModel<P, AlderlakePModel, ProcessorFeatures.SRFFeatures,
ProcessorFeatures.TRMTuning>;
+}
// "Arrandale" along with corei3 and corei5
foreach P = ["nehalem", "corei7", "core_i7_sse4_2"] in {
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 085554f18b2b6b..d46ff07ec7340a 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -162,8 +162,6 @@ constexpr FeatureBitset FeaturesAlderlake =
constexpr FeatureBitset FeaturesSierraforest =
FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
-constexpr FeatureBitset FeaturesGrandridge =
- FeaturesSierraforest | FeatureRAOINT;
constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
constexpr FeatureBitset FeaturesPantherlake =
@@ -369,7 +367,7 @@ constexpr ProcInfo Processors[] = {
// Sierraforest microarchitecture based processors.
{ {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
// Grandridge microarchitecture based processors.
- { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
+ { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
// Granite Rapids microarchitecture based processors.
{ {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
// Granite Rapids D microarchitecture based processors.
|
KanRobert
approved these changes
Dec 27, 2023
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LGTM
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According to latest spec: https://cdrdv2.intel.com/v1/dl/getContent/671368