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AMDGPU: Make v32bf16 a legal type #76679

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Jan 9, 2024
Merged

AMDGPU: Make v32bf16 a legal type #76679

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8c285be
AMDGPU: Make v8bf16/v16bf16 legal types
arsenm Dec 21, 2023
31a74c3
AMDGPU: Make v32bf16 a legal type
arsenm Dec 27, 2023
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16 changes: 9 additions & 7 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -387,18 +387,20 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
MVT::v9i32, MVT::v9f32, MVT::v10i32, MVT::v10f32,
MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32},
Custom);

// FIXME: Why is v8f16/v8bf16 missing?
setOperationAction(
ISD::EXTRACT_SUBVECTOR,
{MVT::v2f16, MVT::v2i16, MVT::v2bf16, MVT::v4f16, MVT::v4i16,
MVT::v4bf16, MVT::v2f32, MVT::v2i32, MVT::v3f32, MVT::v3i32,
{MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4f16, MVT::v4bf16,
MVT::v4i16, MVT::v2f32, MVT::v2i32, MVT::v3f32, MVT::v3i32,
MVT::v4f32, MVT::v4i32, MVT::v5f32, MVT::v5i32, MVT::v6f32,
MVT::v6i32, MVT::v7f32, MVT::v7i32, MVT::v8f32, MVT::v8i32,
MVT::v9f32, MVT::v9i32, MVT::v10i32, MVT::v10f32, MVT::v11i32,
MVT::v11f32, MVT::v12i32, MVT::v12f32, MVT::v16f16, MVT::v16i16,
MVT::v16f32, MVT::v16i32, MVT::v32f32, MVT::v32i32, MVT::v2f64,
MVT::v2i64, MVT::v3f64, MVT::v3i64, MVT::v4f64, MVT::v4i64,
MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64, MVT::v32i16,
MVT::v32f16},
MVT::v11f32, MVT::v12i32, MVT::v12f32, MVT::v16f16, MVT::v16bf16,
MVT::v16i16, MVT::v16f32, MVT::v16i32, MVT::v32f32, MVT::v32i32,
MVT::v2f64, MVT::v2i64, MVT::v3f64, MVT::v3i64, MVT::v4f64,
MVT::v4i64, MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64,
MVT::v32i16, MVT::v32f16, MVT::v32bf16},
Custom);

setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
Expand Down
61 changes: 41 additions & 20 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -167,10 +167,13 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::v4bf16, &AMDGPU::SReg_64RegClass);
addRegisterClass(MVT::v8i16, &AMDGPU::SGPR_128RegClass);
addRegisterClass(MVT::v8f16, &AMDGPU::SGPR_128RegClass);
addRegisterClass(MVT::v8bf16, &AMDGPU::SGPR_128RegClass);
addRegisterClass(MVT::v16i16, &AMDGPU::SGPR_256RegClass);
addRegisterClass(MVT::v16f16, &AMDGPU::SGPR_256RegClass);
addRegisterClass(MVT::v16bf16, &AMDGPU::SGPR_256RegClass);
addRegisterClass(MVT::v32i16, &AMDGPU::SGPR_512RegClass);
addRegisterClass(MVT::v32f16, &AMDGPU::SGPR_512RegClass);
addRegisterClass(MVT::v32bf16, &AMDGPU::SGPR_512RegClass);
}

addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
Expand Down Expand Up @@ -310,13 +313,14 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
// We only support LOAD/STORE and vector manipulation ops for vectors
// with > 4 elements.
for (MVT VT :
{MVT::v8i32, MVT::v8f32, MVT::v9i32, MVT::v9f32, MVT::v10i32,
MVT::v10f32, MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32,
MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64, MVT::v4i16,
MVT::v4f16, MVT::v4bf16, MVT::v3i64, MVT::v3f64, MVT::v6i32,
MVT::v6f32, MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64,
MVT::v8i16, MVT::v8f16, MVT::v16i16, MVT::v16f16, MVT::v16i64,
MVT::v16f64, MVT::v32i32, MVT::v32f32, MVT::v32i16, MVT::v32f16}) {
{MVT::v8i32, MVT::v8f32, MVT::v9i32, MVT::v9f32, MVT::v10i32,
MVT::v10f32, MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32,
MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64, MVT::v4i16,
MVT::v4f16, MVT::v4bf16, MVT::v3i64, MVT::v3f64, MVT::v6i32,
MVT::v6f32, MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64,
MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16,
MVT::v16bf16, MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32,
MVT::v32i16, MVT::v32f16, MVT::v32bf16}) {
for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
switch (Op) {
case ISD::LOAD:
Expand Down Expand Up @@ -683,6 +687,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::LOAD, MVT::v8i16, MVT::v4i32);
setOperationAction(ISD::LOAD, MVT::v8f16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v8f16, MVT::v4i32);
setOperationAction(ISD::LOAD, MVT::v8bf16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v8bf16, MVT::v4i32);

setOperationAction(ISD::STORE, MVT::v4i16, Promote);
AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
Expand All @@ -693,26 +699,36 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::STORE, MVT::v8i16, MVT::v4i32);
setOperationAction(ISD::STORE, MVT::v8f16, Promote);
AddPromotedToType(ISD::STORE, MVT::v8f16, MVT::v4i32);
setOperationAction(ISD::STORE, MVT::v8bf16, Promote);
AddPromotedToType(ISD::STORE, MVT::v8bf16, MVT::v4i32);

setOperationAction(ISD::LOAD, MVT::v16i16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v16i16, MVT::v8i32);
setOperationAction(ISD::LOAD, MVT::v16f16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v16f16, MVT::v8i32);
setOperationAction(ISD::LOAD, MVT::v16bf16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v16bf16, MVT::v8i32);

setOperationAction(ISD::STORE, MVT::v16i16, Promote);
AddPromotedToType(ISD::STORE, MVT::v16i16, MVT::v8i32);
setOperationAction(ISD::STORE, MVT::v16f16, Promote);
AddPromotedToType(ISD::STORE, MVT::v16f16, MVT::v8i32);
setOperationAction(ISD::STORE, MVT::v16bf16, Promote);
AddPromotedToType(ISD::STORE, MVT::v16bf16, MVT::v8i32);

setOperationAction(ISD::LOAD, MVT::v32i16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v32i16, MVT::v16i32);
setOperationAction(ISD::LOAD, MVT::v32f16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v32f16, MVT::v16i32);
setOperationAction(ISD::LOAD, MVT::v32bf16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v32bf16, MVT::v16i32);

setOperationAction(ISD::STORE, MVT::v32i16, Promote);
AddPromotedToType(ISD::STORE, MVT::v32i16, MVT::v16i32);
setOperationAction(ISD::STORE, MVT::v32f16, Promote);
AddPromotedToType(ISD::STORE, MVT::v32f16, MVT::v16i32);
setOperationAction(ISD::STORE, MVT::v32bf16, Promote);
AddPromotedToType(ISD::STORE, MVT::v32bf16, MVT::v16i32);

setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND},
MVT::v2i32, Expand);
Expand All @@ -725,7 +741,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
MVT::v8i32, Expand);

if (!Subtarget->hasVOP3PInsts())
setOperationAction(ISD::BUILD_VECTOR, {MVT::v2i16, MVT::v2f16}, Custom);
setOperationAction(ISD::BUILD_VECTOR,
{MVT::v2i16, MVT::v2f16, MVT::v2bf16}, Custom);

setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
// This isn't really legal, but this avoids the legalizer unrolling it (and
Expand All @@ -743,8 +760,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
{MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
Expand);

for (MVT Vec16 : {MVT::v8i16, MVT::v8f16, MVT::v16i16, MVT::v16f16,
MVT::v32i16, MVT::v32f16}) {
for (MVT Vec16 :
{MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16,
MVT::v16bf16, MVT::v32i16, MVT::v32f16, MVT::v32bf16}) {
setOperationAction(
{ISD::BUILD_VECTOR, ISD::EXTRACT_VECTOR_ELT, ISD::SCALAR_TO_VECTOR},
Vec16, Custom);
Expand Down Expand Up @@ -814,9 +832,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
}

setOperationAction(ISD::SELECT,
{MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8,
MVT::v8i16, MVT::v8f16, MVT::v16i16, MVT::v16f16,
MVT::v32i16, MVT::v32f16},
{MVT::v4i16, MVT::v4f16, MVT::v4bf16, MVT::v2i8, MVT::v4i8,
MVT::v8i8, MVT::v8i16, MVT::v8f16, MVT::v8bf16,
MVT::v16i16, MVT::v16f16, MVT::v16bf16, MVT::v32i16,
MVT::v32f16, MVT::v32bf16},
Custom);

setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom);
Expand Down Expand Up @@ -5389,7 +5408,9 @@ SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,
assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v8i16 ||
VT == MVT::v8f16 || VT == MVT::v4f32 || VT == MVT::v16i16 ||
VT == MVT::v16f16 || VT == MVT::v8f32 || VT == MVT::v16f32 ||
VT == MVT::v32f32 || VT == MVT::v32f16 || VT == MVT::v32i16);
VT == MVT::v32f32 || VT == MVT::v32f16 || VT == MVT::v32i16 ||
VT == MVT::v4bf16 || VT == MVT::v8bf16 || VT == MVT::v16bf16 ||
VT == MVT::v32bf16);

SDValue Lo0, Hi0;
SDValue Op0 = Op.getOperand(0);
Expand Down Expand Up @@ -6812,8 +6833,8 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
SDLoc SL(Op);
EVT VT = Op.getValueType();

if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16 ||
VT == MVT::v8i16 || VT == MVT::v8f16) {
if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v8i16 ||
VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(),
VT.getVectorNumElements() / 2);
MVT HalfIntVT = MVT::getIntegerVT(HalfVT.getSizeInBits());
Expand All @@ -6836,7 +6857,7 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
}

if (VT == MVT::v16i16 || VT == MVT::v16f16) {
if (VT == MVT::v16i16 || VT == MVT::v16f16 || VT == MVT::v16bf16) {
EVT QuarterVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(),
VT.getVectorNumElements() / 4);
MVT QuarterIntVT = MVT::getIntegerVT(QuarterVT.getSizeInBits());
Expand All @@ -6857,7 +6878,7 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
}

if (VT == MVT::v32i16 || VT == MVT::v32f16) {
if (VT == MVT::v32i16 || VT == MVT::v32f16 || VT == MVT::v32bf16) {
EVT QuarterVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(),
VT.getVectorNumElements() / 8);
MVT QuarterIntVT = MVT::getIntegerVT(QuarterVT.getSizeInBits());
Expand Down Expand Up @@ -14140,11 +14161,11 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
EVT VT = N->getValueType(0);

// v2i16 (scalar_to_vector i16:x) -> v2i16 (bitcast (any_extend i16:x))
if (VT == MVT::v2i16 || VT == MVT::v2f16) {
if (VT == MVT::v2i16 || VT == MVT::v2f16 || VT == MVT::v2f16) {
SDLoc SL(N);
SDValue Src = N->getOperand(0);
EVT EltVT = Src.getValueType();
if (EltVT == MVT::f16)
if (EltVT != MVT::i16)
Src = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Src);

SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Src);
Expand Down
88 changes: 88 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1620,6 +1620,37 @@ def : BitConvert <v2f64, v8i16, SReg_128>;
def : BitConvert <v2i64, v8f16, SReg_128>;
def : BitConvert <v2f64, v8f16, SReg_128>;

def : BitConvert <v4i32, v8bf16, SReg_128>;
def : BitConvert <v8bf16, v4i32, SReg_128>;
def : BitConvert <v4i32, v8bf16, VReg_128>;
def : BitConvert <v8bf16, v4i32, VReg_128>;

def : BitConvert <v4f32, v8bf16, SReg_128>;
def : BitConvert <v8bf16, v4f32, SReg_128>;
def : BitConvert <v4f32, v8bf16, VReg_128>;
def : BitConvert <v8bf16, v4f32, VReg_128>;

def : BitConvert <v8i16, v8bf16, SReg_128>;
def : BitConvert <v8bf16, v8i16, SReg_128>;
def : BitConvert <v8i16, v8bf16, VReg_128>;
def : BitConvert <v8bf16, v8i16, VReg_128>;

def : BitConvert <v8f16, v8bf16, SReg_128>;
def : BitConvert <v8bf16, v8f16, SReg_128>;
def : BitConvert <v8f16, v8bf16, VReg_128>;
def : BitConvert <v8bf16, v8f16, VReg_128>;

def : BitConvert <v2f64, v8bf16, SReg_128>;
def : BitConvert <v8bf16, v2f64, SReg_128>;
def : BitConvert <v2f64, v8bf16, VReg_128>;
def : BitConvert <v8bf16, v2f64, VReg_128>;

def : BitConvert <v2i64, v8bf16, SReg_128>;
def : BitConvert <v8bf16, v2i64, SReg_128>;
def : BitConvert <v2i64, v8bf16, VReg_128>;
def : BitConvert <v8bf16, v2i64, VReg_128>;


// 160-bit bitcast
def : BitConvert <v5i32, v5f32, SReg_160>;
def : BitConvert <v5f32, v5i32, SReg_160>;
Expand Down Expand Up @@ -1684,6 +1715,31 @@ def : BitConvert <v4i64, v16i16, VReg_256>;
def : BitConvert <v4f64, v16f16, VReg_256>;
def : BitConvert <v4f64, v16i16, VReg_256>;


def : BitConvert <v8i32, v16bf16, VReg_256>;
def : BitConvert <v16bf16, v8i32, VReg_256>;
def : BitConvert <v8f32, v16bf16, VReg_256>;
def : BitConvert <v16bf16, v8f32, VReg_256>;
def : BitConvert <v4i64, v16bf16, VReg_256>;
def : BitConvert <v16bf16, v4i64, VReg_256>;
def : BitConvert <v4f64, v16bf16, VReg_256>;
def : BitConvert <v16bf16, v4f64, VReg_256>;



def : BitConvert <v16i16, v16bf16, SReg_256>;
def : BitConvert <v16bf16, v16i16, SReg_256>;
def : BitConvert <v16i16, v16bf16, VReg_256>;
def : BitConvert <v16bf16, v16i16, VReg_256>;

def : BitConvert <v16f16, v16bf16, SReg_256>;
def : BitConvert <v16bf16, v16f16, SReg_256>;
def : BitConvert <v16f16, v16bf16, VReg_256>;
def : BitConvert <v16bf16, v16f16, VReg_256>;




// 288-bit bitcast
def : BitConvert <v9i32, v9f32, SReg_288>;
def : BitConvert <v9f32, v9i32, SReg_288>;
Expand Down Expand Up @@ -1732,6 +1788,38 @@ def : BitConvert <v8f64, v16f32, VReg_512>;
def : BitConvert <v16f32, v8i64, VReg_512>;
def : BitConvert <v16f32, v8f64, VReg_512>;



def : BitConvert <v32bf16, v32i16, VReg_512>;
def : BitConvert <v32i16, v32bf16, VReg_512>;
def : BitConvert <v32bf16, v32i16, SReg_512>;
def : BitConvert <v32i16, v32bf16, SReg_512>;

def : BitConvert <v32bf16, v32f16, VReg_512>;
def : BitConvert <v32f16, v32bf16, VReg_512>;
def : BitConvert <v32bf16, v32f16, SReg_512>;
def : BitConvert <v32f16, v32bf16, SReg_512>;

def : BitConvert <v32bf16, v16i32, VReg_512>;
def : BitConvert <v16i32, v32bf16, VReg_512>;
def : BitConvert <v32bf16, v16i32, SReg_512>;
def : BitConvert <v16i32, v32bf16, SReg_512>;

def : BitConvert <v32bf16, v16f32, VReg_512>;
def : BitConvert <v16f32, v32bf16, VReg_512>;
def : BitConvert <v32bf16, v16f32, SReg_512>;
def : BitConvert <v16f32, v32bf16, SReg_512>;

def : BitConvert <v32bf16, v8f64, VReg_512>;
def : BitConvert <v8f64, v32bf16, VReg_512>;
def : BitConvert <v32bf16, v8f64, SReg_512>;
def : BitConvert <v8f64, v32bf16, SReg_512>;

def : BitConvert <v32bf16, v8i64, VReg_512>;
def : BitConvert <v8i64, v32bf16, VReg_512>;
def : BitConvert <v32bf16, v8i64, SReg_512>;
def : BitConvert <v8i64, v32bf16, SReg_512>;

// 1024-bit bitcast
def : BitConvert <v32i32, v32f32, VReg_1024>;
def : BitConvert <v32f32, v32i32, VReg_1024>;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.td
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -916,7 +916,7 @@ defm "" : SRegClass<11, [v11i32, v11f32], SGPR_352Regs, TTMP_352Regs>;
defm "" : SRegClass<12, [v12i32, v12f32], SGPR_384Regs, TTMP_384Regs>;

let GlobalPriority = true in {
defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16], SGPR_512Regs, TTMP_512Regs>;
defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], SGPR_512Regs, TTMP_512Regs>;
defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>;
}

Expand Down Expand Up @@ -970,7 +970,7 @@ defm VReg_352 : VRegClass<11, [v11i32, v11f32], (add VGPR_352)>;
defm VReg_384 : VRegClass<12, [v12i32, v12f32], (add VGPR_384)>;

let GlobalPriority = true in {
defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16], (add VGPR_512)>;
defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], (add VGPR_512)>;
defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>;
}

Expand Down
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