[RISCV] Remove incomplete PRE_DEC/POST_DEC code for XTHeadMemIdx.

[topperc]

As far as I can tell if getIndexedAddressParts received an ISD::SUB, the constant would be negated. So IsInc should be set to true since the SUB was effectively converted to ADD. This means we should never use PRE_DEC/POST_DEC.

No tests are affected because DAGCombine aggressively turns SUB with constant into ADD so no lit test has a SUB reach getIndexedAddressParts.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

As far as I can tell if getIndexedAddressParts received an ISD::SUB, the constant would be negated. So IsInc should be set to true since the SUB was effectively converted to ADD. This means we should never use PRE_DEC/POST_DEC.

No tests are affected because DAGCombine aggressively turns SUB with constant into ADD so no lit test has a SUB reach getIndexedAddressParts.

---

Full diff: https://github.com/llvm/llvm-project/pull/76922.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+4-6)
• (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+3-3)

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index bfa3bf3cc74e2b..befa9e1159bef1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -763,14 +763,12 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
     return false;
 
   EVT LoadVT = Ld->getMemoryVT();
-  bool IsPre = (AM == ISD::PRE_INC || AM == ISD::PRE_DEC);
-  bool IsPost = (AM == ISD::POST_INC || AM == ISD::POST_DEC);
+  assert(AM == ISD::PRE_INC || AM == ISD::POST_INC &&
+         "Unexpected addressing mode");
+  bool IsPre = AM == ISD::PRE_INC;
+  bool IsPost = AM == ISD::POST_INC;
   int64_t Offset = C->getSExtValue();
 
-  // Convert decrements to increments by a negative quantity.
-  if (AM == ISD::PRE_DEC || AM == ISD::POST_DEC)
-    Offset = -Offset;
-
   // The constants that can be encoded in the THeadMemIdx instructions
   // are of the form (sign_extend(imm5) << imm2).
   int64_t Shift;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c8a94adcd91c6a..0a886fe70eeaed 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1350,8 +1350,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   }
 
   if (Subtarget.hasVendorXTHeadMemIdx()) {
-    for (unsigned im = (unsigned)ISD::PRE_INC; im != (unsigned)ISD::POST_DEC;
-         ++im) {
+    for (unsigned im : {ISD::PRE_INC, ISD::POST_INC}) {
       setIndexedLoadAction(im, MVT::i8, Legal);
       setIndexedStoreAction(im, MVT::i8, Legal);
       setIndexedLoadAction(im, MVT::i16, Legal);
@@ -19288,7 +19287,8 @@ bool RISCVTargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
     if (!isLegalIndexedOffset)
       return false;
 
-    IsInc = (Op->getOpcode() == ISD::ADD);
+    // Constant for SUB was negated earlier.
+    IsInc = true;
     Offset = Op->getOperand(1);
     return true;
   }

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[wangpc-pp]

I don't see any error and it seems that AArch64 is the same.
@zixuan-wu Please help double check this, thanks!

[wangpc-pp]

If IsInc is always true, then we don't need this parameter in getIndexedAddressParts.

[ptomsich]

Good catch!

[ptomsich]

Reviewed and LGTM.
I didn't rerun tests, as that was already done by Craig.

[asb]

LGTM.

[wangpc-pp]

LGTM.