[RISCV][GlobalISel] Zbkb support for G_BSWAP #77050

mgudim · 2024-01-05T06:48:17Z

This instructions is legal in the presence of Zbkb extension.

llvmbot · 2024-01-05T06:48:46Z

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-risc-v

Author: Mikhail Gudim (mgudim)

Changes

This instructions is legal in the presence of Zbkb extension.

Full diff: https://github.com/llvm/llvm-project/pull/77050.diff

5 Files Affected:

(modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+1-1)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir (+3)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir (+3)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir (+30-28)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir (+30-28)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 61bae586492584..ab8070772fe543 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -113,7 +113,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
   getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower();
 
   auto &BSWAPActions = getActionDefinitionsBuilder(G_BSWAP);
-  if (ST.hasStdExtZbb())
+  if (ST.hasStdExtZbb() || ST.hasStdExtZbkb())
     BSWAPActions.legalFor({sXLen}).clampScalar(0, sXLen, sXLen);
   else
     BSWAPActions.maxScalar(0, sXLen).lower();
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir
index 733fd128282e04..fd6d7b4163524a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir
@@ -2,6 +2,9 @@
 # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
 # RUN:   -simplify-mir -verify-machineinstrs %s -o - \
 # RUN:   | FileCheck -check-prefix=RV32I %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV32I %s
 
 ---
 name:            bswap_s32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir
index 053abef93a3a17..334d728b64c7be 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir
@@ -2,6 +2,9 @@
 # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
 # RUN:   -simplify-mir -verify-machineinstrs %s -o - \
 # RUN:   | FileCheck -check-prefix=RV64I %s
+# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV64I %s
 
 ---
 name:            bswap_s64
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir
index e66dbfa4c82109..d6598c89b39aff 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir
@@ -2,7 +2,9 @@
 # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
 # RUN:   | FileCheck %s --check-prefix=RV32I
 # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
-# RUN:   | FileCheck %s --check-prefix=RV32ZBB
+# RUN:   | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
+# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \
+# RUN:   | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
 
 ---
 name:            bswap_i16
@@ -23,16 +25,16 @@ body:             |
     ; RV32I-NEXT: $x10 = COPY [[AND]](s32)
     ; RV32I-NEXT: PseudoRET implicit $x10
     ;
-    ; RV32ZBB-LABEL: name: bswap_i16
-    ; RV32ZBB: liveins: $x10
-    ; RV32ZBB-NEXT: {{  $}}
-    ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
-    ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
-    ; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
-    ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; RV32ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
-    ; RV32ZBB-NEXT: $x10 = COPY [[LSHR]](s32)
-    ; RV32ZBB-NEXT: PseudoRET implicit $x10
+    ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i16
+    ; RV32ZBB_OR_RV32ZBKB: liveins: $x10
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: {{  $}}
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[LSHR]](s32)
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = G_ASSERT_ZEXT %0, 16
     %2:_(s16) = G_TRUNC %1(s32)
@@ -65,13 +67,13 @@ body:             |
     ; RV32I-NEXT: $x10 = COPY [[OR2]](s32)
     ; RV32I-NEXT: PseudoRET implicit $x10
     ;
-    ; RV32ZBB-LABEL: name: bswap_i32
-    ; RV32ZBB: liveins: $x10
-    ; RV32ZBB-NEXT: {{  $}}
-    ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
-    ; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
-    ; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
-    ; RV32ZBB-NEXT: PseudoRET implicit $x10
+    ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i32
+    ; RV32ZBB_OR_RV32ZBKB: liveins: $x10
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: {{  $}}
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
     %0:_(s32) = COPY $x10
     %1:_(s32) = G_BSWAP %0
     $x10 = COPY %1(s32)
@@ -115,16 +117,16 @@ body:             |
     ; RV32I-NEXT: $x11 = COPY [[OR5]](s32)
     ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
     ;
-    ; RV32ZBB-LABEL: name: bswap_i64
-    ; RV32ZBB: liveins: $x10, $x11
-    ; RV32ZBB-NEXT: {{  $}}
-    ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
-    ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
-    ; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
-    ; RV32ZBB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
-    ; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
-    ; RV32ZBB-NEXT: $x11 = COPY [[BSWAP1]](s32)
-    ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11
+    ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i64
+    ; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: {{  $}}
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: $x11 = COPY [[BSWAP1]](s32)
+    ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10, implicit $x11
     %0:_(s32) = COPY $x10
     %1:_(s32) = COPY $x11
     %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
index b73a22c1a07eab..10eeff541f8789 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
@@ -2,7 +2,9 @@
 # RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
 # RUN:   | FileCheck %s --check-prefix=RV64I
 # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
-# RUN:   | FileCheck %s --check-prefix=RV64ZBB
+# RUN:   | FileCheck %s --check-prefix=RV64ZBKB
+# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \
+# RUN:   | FileCheck %s --check-prefix=RV64ZBKB
 
 ---
 name:            bswap_i16
@@ -27,16 +29,16 @@ body:             |
     ; RV64I-NEXT: $x10 = COPY [[AND]](s64)
     ; RV64I-NEXT: PseudoRET implicit $x10
     ;
-    ; RV64ZBB-LABEL: name: bswap_i16
-    ; RV64ZBB: liveins: $x10
-    ; RV64ZBB-NEXT: {{  $}}
-    ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
-    ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
-    ; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
-    ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-    ; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
-    ; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64)
-    ; RV64ZBB-NEXT: PseudoRET implicit $x10
+    ; RV64ZBKB-LABEL: name: bswap_i16
+    ; RV64ZBKB: liveins: $x10
+    ; RV64ZBKB-NEXT: {{  $}}
+    ; RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+    ; RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
+    ; RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
+    ; RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+    ; RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
+    ; RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64)
+    ; RV64ZBKB-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $x10
     %1:_(s64) = G_ASSERT_ZEXT %0, 16
     %2:_(s16) = G_TRUNC %1(s64)
@@ -74,16 +76,16 @@ body:             |
     ; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
     ; RV64I-NEXT: PseudoRET implicit $x10
     ;
-    ; RV64ZBB-LABEL: name: bswap_i32
-    ; RV64ZBB: liveins: $x10
-    ; RV64ZBB-NEXT: {{  $}}
-    ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
-    ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
-    ; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
-    ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
-    ; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
-    ; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64)
-    ; RV64ZBB-NEXT: PseudoRET implicit $x10
+    ; RV64ZBKB-LABEL: name: bswap_i32
+    ; RV64ZBKB: liveins: $x10
+    ; RV64ZBKB-NEXT: {{  $}}
+    ; RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+    ; RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
+    ; RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
+    ; RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+    ; RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
+    ; RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64)
+    ; RV64ZBKB-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $x10
     %1:_(s64) = G_ASSERT_ZEXT %0, 32
     %2:_(s32) = G_TRUNC %1(s64)
@@ -132,13 +134,13 @@ body:             |
     ; RV64I-NEXT: $x10 = COPY [[OR6]](s64)
     ; RV64I-NEXT: PseudoRET implicit $x10
     ;
-    ; RV64ZBB-LABEL: name: bswap_i64
-    ; RV64ZBB: liveins: $x10
-    ; RV64ZBB-NEXT: {{  $}}
-    ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
-    ; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]]
-    ; RV64ZBB-NEXT: $x10 = COPY [[BSWAP]](s64)
-    ; RV64ZBB-NEXT: PseudoRET implicit $x10
+    ; RV64ZBKB-LABEL: name: bswap_i64
+    ; RV64ZBKB: liveins: $x10
+    ; RV64ZBKB-NEXT: {{  $}}
+    ; RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+    ; RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]]
+    ; RV64ZBKB-NEXT: $x10 = COPY [[BSWAP]](s64)
+    ; RV64ZBKB-NEXT: PseudoRET implicit $x10
     %0:_(s64) = COPY $x10
     %1:_(s64) = G_BSWAP %0
     $x10 = COPY %1(s64)

topperc · 2024-01-05T06:54:39Z

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir

@@ -2,7 +2,9 @@
 # RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
 # RUN:   | FileCheck %s --check-prefix=RV64I
 # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
-# RUN:   | FileCheck %s --check-prefix=RV64ZBB
+# RUN:   | FileCheck %s --check-prefix=RV64ZBKB


The RV32 check-prefix mentions both extensions, but this only mentions one.

oops. Thanks, fixed.

This instructions is legal in the presence of Zbkb extension.

mgudim · 2024-01-05T07:00:14Z

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir

@@ -2,6 +2,9 @@
 # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
 # RUN:   -simplify-mir -verify-machineinstrs %s -o - \
 # RUN:   | FileCheck -check-prefix=RV32I %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck -check-prefix=RV32I %s


Should we change the prefix here and in 64-bit version also to RV...ZBB_OR_ZBKB?

Sure. Or we could just use the default CHECK

changed to "CHECK"

topperc

LGTM

michaelmaitland · 2024-01-05T21:22:39Z

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir

@@ -2,7 +2,9 @@
 # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
 # RUN:   | FileCheck %s --check-prefix=RV32I
 # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
-# RUN:   | FileCheck %s --check-prefix=RV32ZBB
+# RUN:   | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB


I think these can be simplified to CHECK?

We are checking generated code in two scenarios: when zbb or zbkb is present and when it's not. So I think having these descriptions in the prefix is good.

michaelmaitland · 2024-01-05T21:23:03Z

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir

@@ -2,7 +2,9 @@
 # RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
 # RUN:   | FileCheck %s --check-prefix=RV64I
 # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
-# RUN:   | FileCheck %s --check-prefix=RV64ZBB
+# RUN:   | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB


I think these can be simplified to CHECK?

michaelmaitland · 2024-01-05T21:23:33Z

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir

+# RUN:   | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \
+# RUN:   -simplify-mir -verify-machineinstrs %s -o - \
+# RUN:   | FileCheck %s


Does this need an extra line? It looks like it might fit on the last line

Yep, done. Thanks

michaelmaitland

LGTM

This instructions is legal in the presence of Zbkb extension.

mgudim requested a review from topperc January 5, 2024 06:48

llvmbot added backend:RISC-V llvm:globalisel labels Jan 5, 2024

topperc reviewed Jan 5, 2024

View reviewed changes

[RISCV][GlobalISel] Zbkb support for G_BSWAP

65fc6f3

This instructions is legal in the presence of Zbkb extension.

mgudim force-pushed the bswap branch from 6bd8377 to 65fc6f3 Compare January 5, 2024 06:57

mgudim commented Jan 5, 2024

View reviewed changes

Changed some filckeck prefixes to default "CHECK".

a5dc534

michaelmaitland self-requested a review January 5, 2024 21:21

topperc approved these changes Jan 5, 2024

View reviewed changes

michaelmaitland reviewed Jan 5, 2024

View reviewed changes

Put run commands on the same line.

283702d

michaelmaitland approved these changes Jan 5, 2024

View reviewed changes

Empty commit to restart CI.

32b6b53

mgudim merged commit ba3ef33 into llvm:main Jan 6, 2024
4 checks passed

justinfargnoli pushed a commit to justinfargnoli/llvm-project that referenced this pull request Jan 28, 2024

[RISCV][GlobalISel] Zbkb support for G_BSWAP (llvm#77050)

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[RISCV][GlobalISel] Zbkb support for G_BSWAP #77050

[RISCV][GlobalISel] Zbkb support for G_BSWAP #77050

mgudim commented Jan 5, 2024

llvmbot commented Jan 5, 2024 •

edited

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[RISCV][GlobalISel] Zbkb support for G_BSWAP #77050

[RISCV][GlobalISel] Zbkb support for G_BSWAP #77050

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mgudim commented Jan 5, 2024

llvmbot commented Jan 5, 2024 • edited

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llvmbot commented Jan 5, 2024 •

edited