[Legalizer] Soften EXTRACT_ELEMENT on ppcf128 #77412
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ecnelises
requested review from
jayfoad,
RKSimon,
bzEq,
chenzheng1030,
spavloff and
stefanp-ibm
|
@llvm/pr-subscribers-backend-powerpc @llvm/pr-subscribers-llvm-selectiondag Author: Qiu Chaofan (ecnelises) Changesppc_fp128 values are always split into two f64. Implement soften operation in soft-float mode to handle output f64 correctly. Fixes #76402 Full diff: https://github.com/llvm/llvm-project/pull/77412.diff 3 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 6e0e1e23419bec..69759a7d6471f6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -60,7 +60,9 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
#endif
report_fatal_error("Do not know how to soften the result of this "
"operator!");
-
+ case ISD::EXTRACT_ELEMENT:
+ R = SoftenFloatRes_EXTRACT_ELEMENT(N);
+ break;
case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break;
case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
@@ -262,6 +264,16 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N) {
}
}
+SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) {
+ SDValue Src = N->getOperand(0);
+ assert(Src.getValueType() == MVT::ppcf128 &&
+ Src.getOperand(0)->getOpcode() == ISD::BUILD_PAIR &&
+ "In floats only ppcf128 can be extracted by element!");
+ EVT DestVT = EVT::getIntegerVT(*DAG.getContext(), N->getValueSizeInBits(0));
+ return DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(N), DestVT,
+ Src.getOperand(0), N->getOperand(1));
+}
+
SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 09f0bca8b8611e..efe8ac536b63bd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -541,6 +541,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftenFloatRes_BITCAST(SDNode *N);
SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
SDValue SoftenFloatRes_ConstantFP(SDNode *N);
+ SDValue SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N);
SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
SDValue SoftenFloatRes_FABS(SDNode *N);
SDValue SoftenFloatRes_FMINNUM(SDNode *N);
diff --git a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
index 0ee30f67c30f24..4c74798cf0ea5b 100644
--- a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
@@ -68,8 +68,18 @@ define dso_local zeroext i32 @func(double noundef %0, double noundef %1) #0 {
; CHECK-LABEL: __adddf3
}
+; To check ppc_fp128 soften without crash
+define zeroext i1 @ppcf128_soften(ppc_fp128 %a) #0 {
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %a, i32 100)
+ ret i1 %0
+
+ ; CHECK-LABEL: ppcf128_soften
+}
+
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1
+declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, i32 immarg) #1
attributes #0 = {"use-soft-float"="true" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
|
You can test this locally with the following command:git-clang-format --diff b890c17892c75d1d7671b7c2ba1c927d4d3e09e2 caafabc59f8a4f48774837b953e865aed2ec710b -- llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.hView the diff from clang-format here.diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index ede95557b9..463bd8ea59 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -60,103 +60,200 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
#endif
report_fatal_error("Do not know how to soften the result of this "
"operator!");
- case ISD::EXTRACT_ELEMENT: R = SoftenFloatRes_EXTRACT_ELEMENT(N); break;
- case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break;
- case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
- case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
- case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
- case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N); break;
- case ISD::EXTRACT_VECTOR_ELT:
- R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
- case ISD::FABS: R = SoftenFloatRes_FABS(N); break;
- case ISD::STRICT_FMINNUM:
- case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
- case ISD::STRICT_FMAXNUM:
- case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break;
- case ISD::STRICT_FADD:
- case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
- case ISD::FCBRT: R = SoftenFloatRes_FCBRT(N); break;
- case ISD::STRICT_FCEIL:
- case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
- case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break;
- case ISD::STRICT_FCOS:
- case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break;
- case ISD::STRICT_FDIV:
- case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break;
- case ISD::STRICT_FEXP:
- case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break;
- case ISD::STRICT_FEXP2:
- case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break;
- case ISD::FEXP10: R = SoftenFloatRes_FEXP10(N); break;
- case ISD::STRICT_FFLOOR:
- case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break;
- case ISD::STRICT_FLOG:
- case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break;
- case ISD::STRICT_FLOG2:
- case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break;
- case ISD::STRICT_FLOG10:
- case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break;
- case ISD::STRICT_FMA:
- case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
- case ISD::STRICT_FMUL:
- case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break;
- case ISD::STRICT_FNEARBYINT:
- case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break;
- case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break;
- case ISD::STRICT_FP_EXTEND:
- case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break;
- case ISD::STRICT_FP_ROUND:
- case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break;
- case ISD::FP16_TO_FP: R = SoftenFloatRes_FP16_TO_FP(N); break;
- case ISD::BF16_TO_FP: R = SoftenFloatRes_BF16_TO_FP(N); break;
- case ISD::STRICT_FPOW:
- case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break;
- case ISD::STRICT_FPOWI:
- case ISD::FPOWI:
- case ISD::FLDEXP:
- case ISD::STRICT_FLDEXP: R = SoftenFloatRes_ExpOp(N); break;
- case ISD::FFREXP:
- R = SoftenFloatRes_FFREXP(N);
- break;
- case ISD::STRICT_FREM:
- case ISD::FREM: R = SoftenFloatRes_FREM(N); break;
- case ISD::STRICT_FRINT:
- case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break;
- case ISD::STRICT_FROUND:
- case ISD::FROUND: R = SoftenFloatRes_FROUND(N); break;
- case ISD::STRICT_FROUNDEVEN:
- case ISD::FROUNDEVEN: R = SoftenFloatRes_FROUNDEVEN(N); break;
- case ISD::STRICT_FSIN:
- case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break;
- case ISD::STRICT_FSQRT:
- case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
- case ISD::STRICT_FSUB:
- case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
- case ISD::STRICT_FTRUNC:
- case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break;
- case ISD::LOAD: R = SoftenFloatRes_LOAD(N); break;
- case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
- case ISD::SELECT: R = SoftenFloatRes_SELECT(N); break;
- case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break;
- case ISD::FREEZE: R = SoftenFloatRes_FREEZE(N); break;
- case ISD::STRICT_SINT_TO_FP:
- case ISD::STRICT_UINT_TO_FP:
- case ISD::SINT_TO_FP:
- case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
- case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N); break;
- case ISD::VAARG: R = SoftenFloatRes_VAARG(N); break;
- case ISD::VECREDUCE_FADD:
- case ISD::VECREDUCE_FMUL:
- case ISD::VECREDUCE_FMIN:
- case ISD::VECREDUCE_FMAX:
- case ISD::VECREDUCE_FMAXIMUM:
- case ISD::VECREDUCE_FMINIMUM:
- R = SoftenFloatRes_VECREDUCE(N);
- break;
- case ISD::VECREDUCE_SEQ_FADD:
- case ISD::VECREDUCE_SEQ_FMUL:
- R = SoftenFloatRes_VECREDUCE_SEQ(N);
- break;
+ case ISD::EXTRACT_ELEMENT:
+ R = SoftenFloatRes_EXTRACT_ELEMENT(N);
+ break;
+ case ISD::ARITH_FENCE:
+ R = SoftenFloatRes_ARITH_FENCE(N);
+ break;
+ case ISD::MERGE_VALUES:
+ R = SoftenFloatRes_MERGE_VALUES(N, ResNo);
+ break;
+ case ISD::BITCAST:
+ R = SoftenFloatRes_BITCAST(N);
+ break;
+ case ISD::BUILD_PAIR:
+ R = SoftenFloatRes_BUILD_PAIR(N);
+ break;
+ case ISD::ConstantFP:
+ R = SoftenFloatRes_ConstantFP(N);
+ break;
+ case ISD::EXTRACT_VECTOR_ELT:
+ R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo);
+ break;
+ case ISD::FABS:
+ R = SoftenFloatRes_FABS(N);
+ break;
+ case ISD::STRICT_FMINNUM:
+ case ISD::FMINNUM:
+ R = SoftenFloatRes_FMINNUM(N);
+ break;
+ case ISD::STRICT_FMAXNUM:
+ case ISD::FMAXNUM:
+ R = SoftenFloatRes_FMAXNUM(N);
+ break;
+ case ISD::STRICT_FADD:
+ case ISD::FADD:
+ R = SoftenFloatRes_FADD(N);
+ break;
+ case ISD::FCBRT:
+ R = SoftenFloatRes_FCBRT(N);
+ break;
+ case ISD::STRICT_FCEIL:
+ case ISD::FCEIL:
+ R = SoftenFloatRes_FCEIL(N);
+ break;
+ case ISD::FCOPYSIGN:
+ R = SoftenFloatRes_FCOPYSIGN(N);
+ break;
+ case ISD::STRICT_FCOS:
+ case ISD::FCOS:
+ R = SoftenFloatRes_FCOS(N);
+ break;
+ case ISD::STRICT_FDIV:
+ case ISD::FDIV:
+ R = SoftenFloatRes_FDIV(N);
+ break;
+ case ISD::STRICT_FEXP:
+ case ISD::FEXP:
+ R = SoftenFloatRes_FEXP(N);
+ break;
+ case ISD::STRICT_FEXP2:
+ case ISD::FEXP2:
+ R = SoftenFloatRes_FEXP2(N);
+ break;
+ case ISD::FEXP10:
+ R = SoftenFloatRes_FEXP10(N);
+ break;
+ case ISD::STRICT_FFLOOR:
+ case ISD::FFLOOR:
+ R = SoftenFloatRes_FFLOOR(N);
+ break;
+ case ISD::STRICT_FLOG:
+ case ISD::FLOG:
+ R = SoftenFloatRes_FLOG(N);
+ break;
+ case ISD::STRICT_FLOG2:
+ case ISD::FLOG2:
+ R = SoftenFloatRes_FLOG2(N);
+ break;
+ case ISD::STRICT_FLOG10:
+ case ISD::FLOG10:
+ R = SoftenFloatRes_FLOG10(N);
+ break;
+ case ISD::STRICT_FMA:
+ case ISD::FMA:
+ R = SoftenFloatRes_FMA(N);
+ break;
+ case ISD::STRICT_FMUL:
+ case ISD::FMUL:
+ R = SoftenFloatRes_FMUL(N);
+ break;
+ case ISD::STRICT_FNEARBYINT:
+ case ISD::FNEARBYINT:
+ R = SoftenFloatRes_FNEARBYINT(N);
+ break;
+ case ISD::FNEG:
+ R = SoftenFloatRes_FNEG(N);
+ break;
+ case ISD::STRICT_FP_EXTEND:
+ case ISD::FP_EXTEND:
+ R = SoftenFloatRes_FP_EXTEND(N);
+ break;
+ case ISD::STRICT_FP_ROUND:
+ case ISD::FP_ROUND:
+ R = SoftenFloatRes_FP_ROUND(N);
+ break;
+ case ISD::FP16_TO_FP:
+ R = SoftenFloatRes_FP16_TO_FP(N);
+ break;
+ case ISD::BF16_TO_FP:
+ R = SoftenFloatRes_BF16_TO_FP(N);
+ break;
+ case ISD::STRICT_FPOW:
+ case ISD::FPOW:
+ R = SoftenFloatRes_FPOW(N);
+ break;
+ case ISD::STRICT_FPOWI:
+ case ISD::FPOWI:
+ case ISD::FLDEXP:
+ case ISD::STRICT_FLDEXP:
+ R = SoftenFloatRes_ExpOp(N);
+ break;
+ case ISD::FFREXP:
+ R = SoftenFloatRes_FFREXP(N);
+ break;
+ case ISD::STRICT_FREM:
+ case ISD::FREM:
+ R = SoftenFloatRes_FREM(N);
+ break;
+ case ISD::STRICT_FRINT:
+ case ISD::FRINT:
+ R = SoftenFloatRes_FRINT(N);
+ break;
+ case ISD::STRICT_FROUND:
+ case ISD::FROUND:
+ R = SoftenFloatRes_FROUND(N);
+ break;
+ case ISD::STRICT_FROUNDEVEN:
+ case ISD::FROUNDEVEN:
+ R = SoftenFloatRes_FROUNDEVEN(N);
+ break;
+ case ISD::STRICT_FSIN:
+ case ISD::FSIN:
+ R = SoftenFloatRes_FSIN(N);
+ break;
+ case ISD::STRICT_FSQRT:
+ case ISD::FSQRT:
+ R = SoftenFloatRes_FSQRT(N);
+ break;
+ case ISD::STRICT_FSUB:
+ case ISD::FSUB:
+ R = SoftenFloatRes_FSUB(N);
+ break;
+ case ISD::STRICT_FTRUNC:
+ case ISD::FTRUNC:
+ R = SoftenFloatRes_FTRUNC(N);
+ break;
+ case ISD::LOAD:
+ R = SoftenFloatRes_LOAD(N);
+ break;
+ case ISD::ATOMIC_SWAP:
+ R = BitcastToInt_ATOMIC_SWAP(N);
+ break;
+ case ISD::SELECT:
+ R = SoftenFloatRes_SELECT(N);
+ break;
+ case ISD::SELECT_CC:
+ R = SoftenFloatRes_SELECT_CC(N);
+ break;
+ case ISD::FREEZE:
+ R = SoftenFloatRes_FREEZE(N);
+ break;
+ case ISD::STRICT_SINT_TO_FP:
+ case ISD::STRICT_UINT_TO_FP:
+ case ISD::SINT_TO_FP:
+ case ISD::UINT_TO_FP:
+ R = SoftenFloatRes_XINT_TO_FP(N);
+ break;
+ case ISD::UNDEF:
+ R = SoftenFloatRes_UNDEF(N);
+ break;
+ case ISD::VAARG:
+ R = SoftenFloatRes_VAARG(N);
+ break;
+ case ISD::VECREDUCE_FADD:
+ case ISD::VECREDUCE_FMUL:
+ case ISD::VECREDUCE_FMIN:
+ case ISD::VECREDUCE_FMAX:
+ case ISD::VECREDUCE_FMAXIMUM:
+ case ISD::VECREDUCE_FMINIMUM:
+ R = SoftenFloatRes_VECREDUCE(N);
+ break;
+ case ISD::VECREDUCE_SEQ_FADD:
+ case ISD::VECREDUCE_SEQ_FMUL:
+ R = SoftenFloatRes_VECREDUCE_SEQ(N);
+ break;
}
// If R is null, the sub-method took care of registering the result.
|
arsenm
reviewed
Jan 9, 2024
| SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) { | ||
| SDValue Src = N->getOperand(0); | ||
| assert(Src.getValueType() == MVT::ppcf128 && | ||
| Src.getOperand(0)->getOpcode() == ISD::BUILD_PAIR && |
There was a problem hiding this comment.
Don't think you need the build_pair assertion
| @@ -262,6 +264,16 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N) { | |||
| } | |||
| } | |||
|
|
|||
| SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) { | |||
There was a problem hiding this comment.
In the test case, this is a float operand, not the result? Why does ppcf128 require softening on ppc?
There was a problem hiding this comment.
It's something like
t10: i64 = build_pair t8, t6
t9: i64 = build_pair t4, t2
t11: i128 = build_pair t10, t9
t12: ppcf128 = bitcast t11
t14: f64 = extract_element t12, Constant:i32<1>
t15: i64 = bitcast t14
ppc_fp128 is operand, but result is also a float value which needs soften. Only ppc_fp128 supports extract_element (it consists of two f64s) and result of extracting from ppc_fp128 is f64.
Calling the type ppc_fp128 is because only PPC uses the format, but PPC also does not support it in hardware instruction level, it's always soft.
RKSimon
reviewed
Jan 9, 2024
| assert(Src.getValueType() == MVT::ppcf128 && | ||
| Src.getOperand(0)->getOpcode() == ISD::BUILD_PAIR && | ||
| "In floats only ppcf128 can be extracted by element!"); | ||
| EVT DestVT = EVT::getIntegerVT(*DAG.getContext(), N->getValueSizeInBits(0)); |
There was a problem hiding this comment.
Use EVT::changeTypeToInteger ? But I don't understand why you need to make it an integer
There was a problem hiding this comment.
(see log above) here we are softening float types, they need to be bitcasted to integer as no float register exists in soft float mode
arsenm
reviewed
Jan 10, 2024
| %fpclass = tail call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %a, i32 100) | ||
| ret i1 %fpclass | ||
|
|
||
| ; CHECK-LABEL: ppcf128_soften |
There was a problem hiding this comment.
should check function content not just the label
arsenm
approved these changes
Jan 11, 2024
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O0 < %s | FileCheck %s | ||
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 < %s | FileCheck %s | ||
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 | ||
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -O0 < %s | FileCheck %s --check-prefix=PPC |
There was a problem hiding this comment.
Precommit the switch to generated checks, also don't need -verify-machineinstrs
|
@ecnelises reverse-ping |
ppc_fp128 values are always split into two f64. Implement soften operation in soft-float mode to handle output f64 correctly.
ecnelises
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Sorry, previous patch still crashes under |
RKSimon
reviewed
Apr 4, 2024
| @@ -60,7 +60,9 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { | |||
| #endif | |||
| report_fatal_error("Do not know how to soften the result of this " | |||
| "operator!"); | |||
|
|
|||
| case ISD::EXTRACT_ELEMENT: | |||
| R = SoftenFloatRes_EXTRACT_ELEMENT(N); | |||
There was a problem hiding this comment.
put these on a single line like the rest of the switch (I've committed a9d963f to hopefully stop clang-format warning about this).
There was a problem hiding this comment.
case ISD::EXTRACT_ELEMENT: R = SoftenFloatRes_EXTRACT_ELEMENT(N); break;
case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break;
case ISD::EXTRACT_VECTOR_ELT:
R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;or
case ISD::EXTRACT_ELEMENT:
R = SoftenFloatRes_EXTRACT_ELEMENT(N); break;
case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break;
case ISD::EXTRACT_VECTOR_ELT:
R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;since R cannot be aligned...
There was a problem hiding this comment.
IIRC SoftenFloatRes_EXTRACT_VECTOR_ELT has always been too long - alignment isn't very important tbh, its just about reducing loc as long as its still col80
|
Thanks! |
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ppc_fp128 values are always split into two f64. Implement soften operation in soft-float mode to handle output f64 correctly.
Fixes #76402