Commits on Jan 10, 2024

1. [AArch64] MI Scheduler: create more LDP/STP pairs …

   Target hook `canPairLdStOpc` is missing quite a few opcodes for which
   LDPs/STPs can created. I was hoping that it would not be necessary to
   add these missing opcodes here and that the attached motivating test
   case would be handled by the LoadStoreOptimiser (especially after
    llvm#71908), but it's not. The problem is that after register allocation
   some things are a lot harder to do. Consider this motivating example
   
   [1] renamable $q1 = LDURQi renamable $x9, -16 :: (load (s128) from %ir.r51, align 8, !tbaa !0)
   [2] renamable $q2 = LDURQi renamable $x0, -16 :: (load (s128) from %ir.r53, align 8, !tbaa !4)
   [3] renamable $q1 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMLSv2f64 killed renamable $q1(tied-def 0), killed renamable $q2, renamable $q0, implicit $fpcr
   [4] STURQi killed renamable $q1, renamable $x9, -16 :: (store (s128) into %ir.r51, align 1, !tbaa !0)
   [5] renamable $q1 = LDRQui renamable $x9, 0 :: (load (s128) from %ir.r.G0001_609.0, align 8, !tbaa !0)
   
   We can't combine the the load in line [5] into the load on [1]: regisister q1 is
   used in between. And we can can't combine [1] into [5]: it is aliasing with
   the STR on line [4].
   
   That's why I thought that adding this opcode pair here to the MI scheduler was
   a good compromise.

   

   sjoerdmeijer committed Jan 10, 2024
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