[GlobalIsel][AArch64] more legal icmps #78239

tschuett · 2024-01-16T08:55:01Z

In #78181 the godbolt (https://llvm.godbolt.org/z/vMsnxMf1v) crashed with GlobalIsel.

LLVM ERROR: unable to legalize instruction: %90:(<3 x s32>) = G_ICMP intpred(uge), %15:(<3 x s32>), %0:_ (in function: vec3_i32)

In llvm#78181 the godbolt (https://llvm.godbolt.org/z/vMsnxMf1v) crashed with GlobalIsel. LLVM ERROR: unable to legalize instruction: %90:_(<3 x s32>) = G_ICMP intpred(uge), %15:_(<3 x s32>), %0:_ (in function: vec3_i32)

llvmbot · 2024-01-16T08:55:28Z

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-aarch64

Author: Thorsten Schütt (tschuett)

Changes

In #78181 the godbolt (https://llvm.godbolt.org/z/vMsnxMf1v) crashed with GlobalIsel.

LLVM ERROR: unable to legalize instruction: %90:(<3 x s32>) = G_ICMP intpred(uge), %15:(<3 x s32>), %0:_ (in function: vec3_i32)

Full diff: https://github.com/llvm/llvm-project/pull/78239.diff

3 Files Affected:

(modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+8)
(modified) llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (+6-1)
(modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir (+47-7)

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 91d2497fdb7e20..22df0fd34c057b 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -5314,6 +5314,14 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
     Observer.changedInstr(MI);
     return Legalized;
   }
+  case TargetOpcode::G_ICMP: {
+    Observer.changingInstr(MI);
+    moreElementsVectorSrc(MI, MoreTy, 2);
+    moreElementsVectorSrc(MI, MoreTy, 3);
+    moreElementsVectorDst(MI, MoreTy, 0);
+    Observer.changedInstr(MI);
+    return Legalized;
+  }
   default:
     return UnableToLegalize;
   }
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index e94f9d0c68ffe7..7357d666f1f80b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -524,7 +524,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .minScalarOrEltIf(
           [=](const LegalityQuery &Query) { return Query.Types[1] == v2p0; }, 0,
           s64)
-      .clampNumElements(0, v2s32, v4s32);
+      .moreElementsToNextPow2(0)
+      .clampMaxNumElements(0, s64, 2)
+      .clampMaxNumElements(0, s32, 4)
+      .clampMaxNumElements(0, s16, 8)
+      .clampMaxNumElements(0, s8, 16);
 
   getActionDefinitionsBuilder(G_FCMP)
       // If we don't have full FP16 support, then scalarize the elements of
@@ -863,6 +867,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
           },
           0, s8)
       .minScalarOrElt(0, s8) // Worst case, we need at least s8.
+      .moreElementsToNextPow2(1)
       .clampMaxNumElements(1, s64, 2)
       .clampMaxNumElements(1, s32, 4)
       .clampMaxNumElements(1, s16, 8)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
index e9b3aa0a3a8fd8..b590f8bfd6c111 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
@@ -56,7 +56,9 @@ body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
-  ; CHECK: bb.2:
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %0:_(s128) = G_IMPLICIT_DEF
@@ -93,7 +95,9 @@ body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
-  ; CHECK: bb.2:
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s128) = G_IMPLICIT_DEF
@@ -132,7 +136,9 @@ body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
-  ; CHECK: bb.2:
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s88) = G_IMPLICIT_DEF
@@ -171,7 +177,9 @@ body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
-  ; CHECK: bb.2:
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s88) = G_IMPLICIT_DEF
@@ -210,7 +218,9 @@ body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
-  ; CHECK: bb.2:
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s96) = G_IMPLICIT_DEF
@@ -272,7 +282,9 @@ body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
-  ; CHECK: bb.2:
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s318) = G_IMPLICIT_DEF
@@ -318,7 +330,9 @@ body:             |
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors:
-  ; CHECK: bb.2:
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   RET_ReallyLR
   bb.1:
     %lhs:_(s158) = G_IMPLICIT_DEF
@@ -330,3 +344,29 @@ body:             |
     successors:
   bb.3:
     RET_ReallyLR
+...
+---
+name:            test_3xs32_eq_pr_78181
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x0
+    ; CHECK-LABEL: name: test_3xs32_eq_pr_78181
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %const:_(s32) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
+    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
+    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ICMP]](<4 x s32>), [[C]](s64)
+    ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
+    ; CHECK-NEXT: RET_ReallyLR
+    %const:_(s32) = G_IMPLICIT_DEF
+    %rhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32)
+    %lhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32)
+    %cmp:_(<3 x s32>) = G_ICMP intpred(eq), %lhs(<3 x s32>), %rhs
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s32>), %1(s32)
+    $w0 = COPY %2(s32)
+    RET_ReallyLR

arsenm · 2024-01-16T10:23:04Z

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

+    %const:_(s32) = G_IMPLICIT_DEF
+    %rhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32)
+    %lhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32)
+    %cmp:_(<3 x s32>) = G_ICMP intpred(eq), %lhs(<3 x s32>), %rhs


Test vectors of all the touched element types?

I am confused. The error was that it failed to legalize <3 x s32>.

But you changed clampMaxNumElements on more element types than that

I use now clampNumElements to limit lower and upper bound. There are now some clamp tests.

fix tests

tschuett · 2024-01-16T15:00:35Z

llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir

    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[UV]](<2 x s32>), [[UV3]](<2 x s32>)


improved legalization of G_EXTRACT_VECTOR_ELT.

tschuett · 2024-01-16T15:01:11Z

llvm/test/CodeGen/AArch64/arm64-vabs.ll

-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_8b
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_16b
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_4h
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_8h


no fallbacks, but code differences.

tschuett · 2024-01-16T15:01:42Z

llvm/test/CodeGen/AArch64/icmp.ll

@@ -2,12 +2,6 @@
 ; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
 ; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

-; CHECK-GI:       warning: Instruction selection used fallback path for v3i64_i64
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for v4i64_i64
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for v3i32_i32


no fallbacks, but code differences.

tschuett · 2024-01-16T15:02:28Z

llvm/test/CodeGen/AArch64/icmp.ll

+; CHECK-SD-NEXT:    cmgt v0.8h, v2.8h, v0.8h
+; CHECK-SD-NEXT:    bsl v1.16b, v5.16b, v7.16b
+; CHECK-SD-NEXT:    bsl v0.16b, v4.16b, v6.16b
+; CHECK-SD-NEXT:    ret


They look the same. The order of cmgt differs.

davemgreen

The ICmp part looks OK to me so long as we have proper testing for it (which I added a little while ago).

davemgreen · 2024-01-16T15:16:45Z

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -863,6 +867,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
          },
          0, s8)
      .minScalarOrElt(0, s8) // Worst case, we need at least s8.
+      .moreElementsToNextPow2(1)


ExtractVector should probably be in a separate pr. I was looking into some of the vector operations a little while ago, but I think that still needs cleaning up a bit. I had a patch for fcmp too which I will try and upload.

I need the change for the icmp tests.

I see, because they extract a single lane for the tests. It sounds harmless enough to keep then.

davemgreen · 2024-01-16T15:17:20Z

llvm/test/CodeGen/AArch64/arm64-vabs.ll

@@ -2,21 +2,6 @@
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck -check-prefixes=CHECK,CHECK-SD %s
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

-; CHECK-GI:       warning: Instruction selection used fallback path for uabd16b_rdx


Can all of these really be removed? If so you can remove the -global-isel-abort=2 from the command line.

This can still be:

; CHECK-GI: warning: Instruction selection used fallback path for abs_8b ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_16b ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_4h ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_8h ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_2s ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_4s ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_1d ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_1d_honestly ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabds ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabdd ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uabd_i64

davemgreen · 2024-01-16T15:19:38Z

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

+    Observer.changingInstr(MI);
+    moreElementsVectorSrc(MI, MoreTy, 2);
+    moreElementsVectorSrc(MI, MoreTy, 3);
+    moreElementsVectorDst(MI, MoreTy, 0);


I'm not sure how much this matters, but this looks like it is assuming that the three types are all the same, not that one is a predicate vector (i1 elements). Neon will work with full vector lane mask results, so it should work OK there, but possible not for other architectures with vector predicate register like SVE and MVE.

That is a good point. I should be the SrcTy.

The MoreTy comes from here:

llvm-project/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Line 5155 in c1a4424

LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,

Properly supporting predicates will take more work.

It might need to be similar to the trunc code:

llvm-project/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Line 5309 in c1a4424

LLT SrcTy = LLT::fixed_vector(

, but it might be better to wait until a vector target needs it, and just add a TODO at the moment?

Furthermore, SVE and moreElements is incompatible. I cannot change the length of a scalable vector.

davemgreen · 2024-01-16T18:21:29Z

llvm/test/CodeGen/AArch64/icmp.ll

@@ -2,12 +2,6 @@
 ; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
 ; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI


Can this remove -global-isel-abort=2 now?

I would prefer to solve that issue in a different PR. I got failures without global-isel-abort:

LLVM ERROR: unable to legalize instruction: %31:_(<3 x s32>) = G_ASHR %99:_, %101:_(<3 x s32>) (in function: v3i32_i32)

Shouldn't some of the "fallback" lines remain then?

I restored the fallback. I will look into G_ASHR.

davemgreen

If you can update the fallback lines in the vabs test then this LGTM. I can rebase the fcmp patch I have on top of it, and hopefully make use of the LegalizerHelper change. Thanks

davemgreen · 2024-01-17T11:14:33Z

llvm/test/CodeGen/AArch64/arm64-vabs.ll

@@ -2,21 +2,6 @@
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck -check-prefixes=CHECK,CHECK-SD %s
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

-; CHECK-GI:       warning: Instruction selection used fallback path for uabd16b_rdx


This can still be:

; CHECK-GI: warning: Instruction selection used fallback path for abs_8b ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_16b ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_4h ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_8h ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_2s ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_4s ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_1d ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_1d_honestly ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabds ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabdd ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uabd_i64

In llvm#78181 the godbolt (https://llvm.godbolt.org/z/vMsnxMf1v) crashed with GlobalIsel. LLVM ERROR: unable to legalize instruction: %90:_(<3 x s32>) = G_ICMP intpred(uge), %15:_(<3 x s32>), %0:_ (in function: vec3_i32)

[GlobalIsel][AArch64] more legal icmps

e51001f

In llvm#78181 the godbolt (https://llvm.godbolt.org/z/vMsnxMf1v) crashed with GlobalIsel. LLVM ERROR: unable to legalize instruction: %90:_(<3 x s32>) = G_ICMP intpred(uge), %15:_(<3 x s32>), %0:_ (in function: vec3_i32)

tschuett requested a review from aemerson January 16, 2024 08:55

llvmbot added backend:AArch64 llvm:globalisel labels Jan 16, 2024

arsenm reviewed Jan 16, 2024

View reviewed changes

improve icmp legalization

18524de

fix tests

tschuett commented Jan 16, 2024

View reviewed changes

davemgreen reviewed Jan 16, 2024

View reviewed changes

tschuett added 2 commits January 16, 2024 17:41

add todo to moreElements

e3021e2

fix typo

da1d8e1

davemgreen reviewed Jan 16, 2024

View reviewed changes

document fallback in icmp.ll

4d6c6a2

davemgreen approved these changes Jan 17, 2024

View reviewed changes

restore fallbacks in arm64-vabs

6955ac3

davemgreen approved these changes Jan 17, 2024

View reviewed changes

trigger CI

5dd7e9e

tschuett merged commit 67dc6e9 into llvm:main Jan 17, 2024
3 of 4 checks passed

tschuett deleted the gisel-leglize-cmps2 branch January 17, 2024 21:23

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[GlobalIsel][AArch64] more legal icmps #78239

[GlobalIsel][AArch64] more legal icmps #78239

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		; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
		; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[UV]](<2 x s32>), [[UV3]](<2 x s32>)

		@@ -2,12 +2,6 @@
		; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - \| FileCheck %s --check-prefixes=CHECK,CHECK-SD
		; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 \| FileCheck %s --check-prefixes=CHECK,CHECK-GI

[GlobalIsel][AArch64] more legal icmps #78239

[GlobalIsel][AArch64] more legal icmps #78239

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tschuett commented Jan 16, 2024

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