[X86][MC] Support encoding optimization & assembler relaxation about immediate operands for APX instructions #78545
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Wait... I think this should be landed after all NDD instructions are supported. |
KanRobert
reviewed
Jan 23, 2024
Comment on lines
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| ENTRY(ADC16mi_ND, ADC16mi8_ND) | ||
| ENTRY(ADC16ri_ND, ADC16ri8_ND) | ||
| ENTRY(ADC32mi_ND, ADC32mi8_ND) | ||
| ENTRY(ADC32ri_ND, ADC32ri8_ND) | ||
| ENTRY(ADC64mi32_ND, ADC64mi8_ND) | ||
| ENTRY(ADC64ri32_ND, ADC64ri8_ND) |
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Need to support for shift/rotate instructions too.
|
I remember we have separate tests for encoding optimization for APX. |
Seems yes, I forgot that :(, then --show-mc-encoding is not that necessary. |
We can keep it for NDD2NonDD compress |
XinWang10
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KanRobert
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KanRobert
changed the title
KanRobert
reviewed
Jan 26, 2024
|
@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-x86 Author: None (XinWang10) ChangesEncoding optimization: if the immediate operand is 8-bit wide. Assembler relaxation: If the immediate operand is a symbol expression and it's value is unknown. Patch is 91.14 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/78545.diff 28 Files Affected:
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
index 03eeef96b502e0d..134206466c542fe 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
@@ -106,6 +106,12 @@ bool X86::optimizeShiftRotateWithImmediateOne(MCInst &MI) {
#define TO_IMM1(FROM) \
case X86::FROM##i: \
NewOpc = X86::FROM##1; \
+ break; \
+ case X86::FROM##i_EVEX: \
+ NewOpc = X86::FROM##1_EVEX; \
+ break; \
+ case X86::FROM##i_ND: \
+ NewOpc = X86::FROM##1_ND; \
break;
switch (MI.getOpcode()) {
default:
@@ -118,6 +124,31 @@ bool X86::optimizeShiftRotateWithImmediateOne(MCInst &MI) {
TO_IMM1(RCL16r)
TO_IMM1(RCL32r)
TO_IMM1(RCL64r)
+ TO_IMM1(RCR8m)
+ TO_IMM1(RCR16m)
+ TO_IMM1(RCR32m)
+ TO_IMM1(RCR64m)
+ TO_IMM1(RCL8m)
+ TO_IMM1(RCL16m)
+ TO_IMM1(RCL32m)
+ TO_IMM1(RCL64m)
+#undef TO_IMM1
+#define TO_IMM1(FROM) \
+ case X86::FROM##i: \
+ NewOpc = X86::FROM##1; \
+ break; \
+ case X86::FROM##i_EVEX: \
+ NewOpc = X86::FROM##1_EVEX; \
+ break; \
+ case X86::FROM##i_NF: \
+ NewOpc = X86::FROM##1_NF; \
+ break; \
+ case X86::FROM##i_ND: \
+ NewOpc = X86::FROM##1_ND; \
+ break; \
+ case X86::FROM##i_NF_ND: \
+ NewOpc = X86::FROM##1_NF_ND; \
+ break;
TO_IMM1(ROR8r)
TO_IMM1(ROR16r)
TO_IMM1(ROR32r)
@@ -138,14 +169,6 @@ bool X86::optimizeShiftRotateWithImmediateOne(MCInst &MI) {
TO_IMM1(SHL16r)
TO_IMM1(SHL32r)
TO_IMM1(SHL64r)
- TO_IMM1(RCR8m)
- TO_IMM1(RCR16m)
- TO_IMM1(RCR32m)
- TO_IMM1(RCR64m)
- TO_IMM1(RCL8m)
- TO_IMM1(RCL16m)
- TO_IMM1(RCL32m)
- TO_IMM1(RCL64m)
TO_IMM1(ROR8m)
TO_IMM1(ROR16m)
TO_IMM1(ROR32m)
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
index e475e55260ed36a..27b6a654e6eb7fa 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def
@@ -12,61 +12,78 @@
#ifndef ENTRY
#define ENTRY(LONG, SHORT)
#endif
-ENTRY(ADC16mi, ADC16mi8)
-ENTRY(ADC16ri, ADC16ri8)
-ENTRY(ADC32mi, ADC32mi8)
-ENTRY(ADC32ri, ADC32ri8)
-ENTRY(ADC64mi32, ADC64mi8)
-ENTRY(ADC64ri32, ADC64ri8)
-ENTRY(SBB16mi, SBB16mi8)
-ENTRY(SBB16ri, SBB16ri8)
-ENTRY(SBB32mi, SBB32mi8)
-ENTRY(SBB32ri, SBB32ri8)
-ENTRY(SBB64mi32, SBB64mi8)
-ENTRY(SBB64ri32, SBB64ri8)
-ENTRY(ADD16mi, ADD16mi8)
-ENTRY(ADD16ri, ADD16ri8)
-ENTRY(ADD32mi, ADD32mi8)
-ENTRY(ADD32ri, ADD32ri8)
-ENTRY(ADD64mi32, ADD64mi8)
-ENTRY(ADD64ri32, ADD64ri8)
-ENTRY(AND16mi, AND16mi8)
-ENTRY(AND16ri, AND16ri8)
-ENTRY(AND32mi, AND32mi8)
-ENTRY(AND32ri, AND32ri8)
-ENTRY(AND64mi32, AND64mi8)
-ENTRY(AND64ri32, AND64ri8)
-ENTRY(OR16mi, OR16mi8)
-ENTRY(OR16ri, OR16ri8)
-ENTRY(OR32mi, OR32mi8)
-ENTRY(OR32ri, OR32ri8)
-ENTRY(OR64mi32, OR64mi8)
-ENTRY(OR64ri32, OR64ri8)
-ENTRY(SUB16mi, SUB16mi8)
-ENTRY(SUB16ri, SUB16ri8)
-ENTRY(SUB32mi, SUB32mi8)
-ENTRY(SUB32ri, SUB32ri8)
-ENTRY(SUB64mi32, SUB64mi8)
-ENTRY(SUB64ri32, SUB64ri8)
-ENTRY(XOR16mi, XOR16mi8)
-ENTRY(XOR16ri, XOR16ri8)
-ENTRY(XOR32mi, XOR32mi8)
-ENTRY(XOR32ri, XOR32ri8)
-ENTRY(XOR64mi32, XOR64mi8)
-ENTRY(XOR64ri32, XOR64ri8)
ENTRY(CMP16mi, CMP16mi8)
ENTRY(CMP16ri, CMP16ri8)
ENTRY(CMP32mi, CMP32mi8)
ENTRY(CMP32ri, CMP32ri8)
ENTRY(CMP64mi32, CMP64mi8)
ENTRY(CMP64ri32, CMP64ri8)
-ENTRY(IMUL16rmi, IMUL16rmi8)
-ENTRY(IMUL16rri, IMUL16rri8)
-ENTRY(IMUL32rmi, IMUL32rmi8)
-ENTRY(IMUL32rri, IMUL32rri8)
-ENTRY(IMUL64rmi32, IMUL64rmi8)
-ENTRY(IMUL64rri32, IMUL64rri8)
ENTRY(PUSH16i, PUSH16i8)
ENTRY(PUSH32i, PUSH32i8)
ENTRY(PUSH64i32, PUSH64i8)
+#define ENTRYS(LONG, SHORT) \
+ ENTRY(LONG, SHORT) \
+ ENTRY(LONG##_EVEX, SHORT##_EVEX) \
+ ENTRY(LONG##_NF, SHORT##_NF) \
+ ENTRY(LONG##_ND, SHORT##_ND) \
+ ENTRY(LONG##_NF_ND, SHORT##_NF_ND)
+ENTRYS(ADD16mi, ADD16mi8)
+ENTRYS(ADD16ri, ADD16ri8)
+ENTRYS(ADD32mi, ADD32mi8)
+ENTRYS(ADD32ri, ADD32ri8)
+ENTRYS(ADD64mi32, ADD64mi8)
+ENTRYS(ADD64ri32, ADD64ri8)
+ENTRYS(AND16mi, AND16mi8)
+ENTRYS(AND16ri, AND16ri8)
+ENTRYS(AND32mi, AND32mi8)
+ENTRYS(AND32ri, AND32ri8)
+ENTRYS(AND64mi32, AND64mi8)
+ENTRYS(AND64ri32, AND64ri8)
+ENTRYS(OR16mi, OR16mi8)
+ENTRYS(OR16ri, OR16ri8)
+ENTRYS(OR32mi, OR32mi8)
+ENTRYS(OR32ri, OR32ri8)
+ENTRYS(OR64mi32, OR64mi8)
+ENTRYS(OR64ri32, OR64ri8)
+ENTRYS(SUB16mi, SUB16mi8)
+ENTRYS(SUB16ri, SUB16ri8)
+ENTRYS(SUB32mi, SUB32mi8)
+ENTRYS(SUB32ri, SUB32ri8)
+ENTRYS(SUB64mi32, SUB64mi8)
+ENTRYS(SUB64ri32, SUB64ri8)
+ENTRYS(XOR16mi, XOR16mi8)
+ENTRYS(XOR16ri, XOR16ri8)
+ENTRYS(XOR32mi, XOR32mi8)
+ENTRYS(XOR32ri, XOR32ri8)
+ENTRYS(XOR64mi32, XOR64mi8)
+ENTRYS(XOR64ri32, XOR64ri8)
+#undef ENTRYS
+#define ENTRYS(LONG, SHORT) \
+ ENTRY(LONG, SHORT) \
+ ENTRY(LONG##_EVEX, SHORT##_EVEX) \
+ ENTRY(LONG##_NF, SHORT##_NF)
+ENTRYS(IMUL16rmi, IMUL16rmi8)
+ENTRYS(IMUL16rri, IMUL16rri8)
+ENTRYS(IMUL32rmi, IMUL32rmi8)
+ENTRYS(IMUL32rri, IMUL32rri8)
+ENTRYS(IMUL64rmi32, IMUL64rmi8)
+ENTRYS(IMUL64rri32, IMUL64rri8)
+#undef ENTRYS
+#define ENTRYS(LONG, SHORT) \
+ ENTRY(LONG, SHORT) \
+ ENTRY(LONG##_EVEX, SHORT##_EVEX) \
+ ENTRY(LONG##_ND, SHORT##_ND)
+ENTRYS(ADC16mi, ADC16mi8)
+ENTRYS(ADC16ri, ADC16ri8)
+ENTRYS(ADC32mi, ADC32mi8)
+ENTRYS(ADC32ri, ADC32ri8)
+ENTRYS(ADC64mi32, ADC64mi8)
+ENTRYS(ADC64ri32, ADC64ri8)
+ENTRYS(SBB16mi, SBB16mi8)
+ENTRYS(SBB16ri, SBB16ri8)
+ENTRYS(SBB32mi, SBB32mi8)
+ENTRYS(SBB32ri, SBB32ri8)
+ENTRYS(SBB64mi32, SBB64mi8)
+ENTRYS(SBB64ri32, SBB64ri8)
+#undef ENTRYS
#undef ENTRY
diff --git a/llvm/test/CodeGen/X86/apx/adc.ll b/llvm/test/CodeGen/X86/apx/adc.ll
index 342d64e6bca009c..621784f86bdedbd 100644
--- a/llvm/test/CodeGen/X86/apx/adc.ll
+++ b/llvm/test/CodeGen/X86/apx/adc.ll
@@ -113,7 +113,7 @@ define i16 @adc16ri8(i16 %a, i16 %x, i16 %y) nounwind {
; CHECK-LABEL: adc16ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT: adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xd7,0x00,0x00]
+; CHECK-NEXT: adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xd7,0x00]
; CHECK-NEXT: addl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x7b]
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -128,7 +128,7 @@ define i32 @adc32ri8(i32 %a, i32 %x, i32 %y) nounwind {
; CHECK-LABEL: adc32ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT: adcl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xd7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: adcl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xd7,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
%s = add i32 %a, 123
%k = icmp ugt i32 %x, %y
@@ -141,7 +141,7 @@ define i64 @adc64ri8(i64 %a, i64 %x, i64 %y) nounwind {
; CHECK-LABEL: adc64ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT: adcq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xd7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: adcq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xd7,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
%s = add i64 %a, 123
%k = icmp ugt i64 %x, %y
@@ -167,7 +167,7 @@ define i16 @adc16ri(i16 %a, i16 %x, i16 %y) nounwind {
; CHECK-LABEL: adc16ri:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT: adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xd7,0x00,0x00]
+; CHECK-NEXT: adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xd7,0x00]
; CHECK-NEXT: addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
; CHECK-NEXT: # imm = 0x4D2
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
@@ -267,7 +267,7 @@ define i16 @adc16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
; CHECK-LABEL: adc16mi8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT: adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT: adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
; CHECK-NEXT: addl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x7b]
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -283,7 +283,7 @@ define i32 @adc32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
; CHECK-LABEL: adc32mi8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT: adcl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x17,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: adcl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x17,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
%a = load i32, ptr %ptr
%s = add i32 %a, 123
@@ -297,7 +297,7 @@ define i64 @adc64mi8(ptr %ptr, i64 %x, i64 %y) nounwind {
; CHECK-LABEL: adc64mi8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT: adcq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x17,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: adcq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x17,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
%a = load i64, ptr %ptr
%s = add i64 %a, 123
@@ -325,7 +325,7 @@ define i16 @adc16mi(ptr %ptr, i16 %x, i16 %y) nounwind {
; CHECK-LABEL: adc16mi:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT: adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT: adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
; CHECK-NEXT: addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
; CHECK-NEXT: # imm = 0x4D2
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
@@ -447,7 +447,7 @@ define void @adc16mi_legacy(ptr %ptr, i16 %x, i16 %y) nounwind {
; CHECK-LABEL: adc16mi_legacy:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT: adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT: adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
; CHECK-NEXT: addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
; CHECK-NEXT: # imm = 0x4D2
; CHECK-NEXT: movw %ax, (%rdi) # encoding: [0x66,0x89,0x07]
diff --git a/llvm/test/CodeGen/X86/apx/add.ll b/llvm/test/CodeGen/X86/apx/add.ll
index a42f872b93e16fa..cdb29a70770e4b4 100644
--- a/llvm/test/CodeGen/X86/apx/add.ll
+++ b/llvm/test/CodeGen/X86/apx/add.ll
@@ -89,7 +89,7 @@ entry:
define i16 @add16ri8(i16 noundef %a) {
; CHECK-LABEL: add16ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xc7,0x7b]
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
@@ -100,7 +100,7 @@ entry:
define i32 @add32ri8(i32 noundef %a) {
; CHECK-LABEL: add32ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xc7,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%add = add i32 %a, 123
@@ -110,7 +110,7 @@ entry:
define i64 @add64ri8(i64 noundef %a) {
; CHECK-LABEL: add64ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: addq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xc7,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%add = add i64 %a, 123
@@ -221,7 +221,7 @@ entry:
define i32 @add32mi8(ptr %a) {
; CHECK-LABEL: add32mi8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x07,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: addl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x07,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
@@ -232,7 +232,7 @@ entry:
define i64 @add64mi8(ptr %a) {
; CHECK-LABEL: add64mi8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x07,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: addq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x07,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
@@ -405,7 +405,7 @@ entry:
define i16 @addflag16ri8(i16 noundef %a) {
; CHECK-LABEL: addflag16ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addw $123, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xc7,0x7b,0x00]
+; CHECK-NEXT: addw $123, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xc7,0x7b]
; CHECK-NEXT: movl $65535, %eax # encoding: [0xb8,0xff,0xff,0x00,0x00]
; CHECK-NEXT: # imm = 0xFFFF
; CHECK-NEXT: cmovael %ecx, %eax # encoding: [0x0f,0x43,0xc1]
@@ -419,7 +419,7 @@ entry:
define i32 @addflag32ri8(i32 noundef %a) {
; CHECK-LABEL: addflag32ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: addl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xc7,0x7b]
; CHECK-NEXT: movl $-1, %eax # encoding: [0xb8,0xff,0xff,0xff,0xff]
; CHECK-NEXT: cmovael %ecx, %eax # encoding: [0x0f,0x43,0xc1]
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -431,7 +431,7 @@ entry:
define i64 @addflag64ri8(i64 noundef %a) {
; CHECK-LABEL: addflag64ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: addq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xc7,0x7b]
; CHECK-NEXT: movq $-1, %rax # encoding: [0x48,0xc7,0xc0,0xff,0xff,0xff,0xff]
; CHECK-NEXT: cmovaeq %rcx, %rax # encoding: [0x48,0x0f,0x43,0xc1]
; CHECK-NEXT: retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/apx/and.ll b/llvm/test/CodeGen/X86/apx/and.ll
index b7c1a851c07d634..af8f4119ac054d3 100644
--- a/llvm/test/CodeGen/X86/apx/and.ll
+++ b/llvm/test/CodeGen/X86/apx/and.ll
@@ -90,7 +90,7 @@ entry:
define i16 @and16ri8(i16 noundef %a) {
; CHECK-LABEL: and16ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
@@ -101,7 +101,7 @@ entry:
define i32 @and32ri8(i32 noundef %a) {
; CHECK-LABEL: and32ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%and = and i32 %a, 123
@@ -111,7 +111,7 @@ entry:
define i64 @and64ri8(i64 noundef %a) {
; CHECK-LABEL: and64ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%and = and i64 %a, 123
@@ -222,7 +222,7 @@ entry:
define i32 @and32mi8(ptr %a) {
; CHECK-LABEL: and32mi8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x27,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: andl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x27,0x7b]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
@@ -482,7 +482,7 @@ define i1 @andflag64ri(i64 %a) {
define i1 @andflag16ri8(i16 %a) {
; CHECK-LABEL: andflag16ri8:
; CHECK: # %bb.0:
-; CHECK-NEXT: andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xe7,0x84,0xff]
+; CHECK-NEXT: andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xe7,0x84]
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
@@ -497,7 +497,7 @@ define i1 @andflag16ri8(i16 %a) {
define i1 @andflag32ri8(i32 %a) {
; CHECK-LABEL: andflag32ri8:
; CHECK: # %bb.0:
-; CHECK-NEXT: andl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: andl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xe7,0x7b]
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
@@ -511,7 +511,7 @@ define i1 @andflag32ri8(i32 %a) {
define i1 @andflag64ri8(i64 %a) {
; CHECK-LABEL: andflag64ri8:
; CHECK: # %bb.0:
-; CHECK-NEXT: andq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: andq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xe7,0x7b]
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
diff --git a/llvm/test/CodeGen/X86/apx/or.ll b/llvm/test/CodeGen/X86/apx/or.ll
index 1219e74074a96dd..3d024e962400fad 100644
--- a/llvm/test/CodeGen/X86/apx/or.ll
+++ b/llvm/test/CodeGen/X86/apx/or.ll
@@ -90,7 +90,7 @@ entry:
define i16 @or16ri8(i16 noundef %a) {
; CHECK-LABEL: or16ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT: orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xcf,0x7b]
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
@@ -101,7 +101,7 @@ entry:
define i32 @or32ri8(i32 noundef %a) {
; CHECK-LABEL: or32ri8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xcf,0x7b...
[truncated]
|
|
Thanks |
|
This is causing: |
|
I think @XinWang10 forgot to update it. |
KanRobert
added a commit
that referenced
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Jan 30, 2024
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Encoding optimization:
if the immediate operand is 8-bit wide.
Assembler relaxation:
If the immediate operand is a symbol expression and it's value is unknown.