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[ARM] Resolve FIXME: Swap adds <-> subs offset is 0 #78870
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@llvm/pr-subscribers-backend-arm Author: AtariDreams (AtariDreams) ChangesAlso erase instruction if offset is 0 Full diff: https://github.com/llvm/llvm-project/pull/78870.diff 1 Files Affected:
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index ed9d30c3c3ab90..10478611497a08 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -525,13 +525,19 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
// Merge it with the update; if the merged offset is too large,
// insert a new sub instead.
MachineOperand &MO =
- MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
- Offset = (Opc == ARM::tSUBi8) ?
- MO.getImm() + WordOffset * 4 :
- MO.getImm() - WordOffset * 4 ;
- if (Offset >= 0 && TL->isLegalAddImmediate(Offset)) {
- // FIXME: Swap ADDS<->SUBS if Offset < 0, erase instruction if
- // Offset == 0.
+ MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
+ Offset = (Opc == ARM::tSUBi8) ? MO.getImm() + WordOffset * 4
+ : MO.getImm() - WordOffset * 4;
+ if (TL->isLegalAddImmediate(Offset)) {
+ if (Offset < 0) {
+ // Swap ADDS<->SUBS if Offset < 0
+ Opc = (Opc == ARM::tSUBi8) ? ARM::tADDi8 : ARM::tSUBi8;
+ Offset = -Offset;
+ } else if (Offset == 0) {
+ // Erase instruction if Offset == 0
+ MBBI = MBB.erase(MBBI);
+ return;
+ }
MO.setImm(Offset);
// The base register has now been reset, so exit early.
return;
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
Do you have tests cases for where this can come up? I'm not sure we should be generating instructions with negative offsets. |
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Also erase instruction if offset is 0.
Also erase instruction if offset is 0.