[MC][X86] Merge lane/element broadcast comment printers. #79020
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@llvm/pr-subscribers-backend-x86 Author: Simon Pilgrim (RKSimon) ChangesThis is /almost/ NFC - the only annoyance is that for some reason we were using "<C1,C2,..>" for ConstantVector types unlike all other cases - these now use the same "[C1,C2,..]" format as the other constant printers. I don't think we have any reason to keep this diff, but I'm putting up this PR just in case there's a reason I've forgotten. Patch is 2.05 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/79020.diff 112 Files Affected:
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 8bf099a1658169..87918838744b60 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1575,68 +1575,18 @@ static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer,
OutStreamer.AddComment(CS.str());
}
-static void printLaneBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer,
- int NumLanes, int BitWidth) {
- if (auto *C = X86::getConstantFromPool(*MI, 1)) {
- int CstEltSize = C->getType()->getScalarSizeInBits();
-
- std::string Comment;
- raw_string_ostream CS(Comment);
- const MachineOperand &DstOp = MI->getOperand(0);
- CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
- if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
- int NumElements = CDS->getNumElements();
- if ((BitWidth % CstEltSize) == 0)
- NumElements = std::min<int>(NumElements, BitWidth / CstEltSize);
- CS << "[";
- for (int l = 0; l != NumLanes; ++l) {
- for (int i = 0; i < NumElements; ++i) {
- if (i != 0 || l != 0)
- CS << ",";
- if (CDS->getElementType()->isIntegerTy())
- printConstant(CDS->getElementAsAPInt(i), CS);
- else if (CDS->getElementType()->isHalfTy() ||
- CDS->getElementType()->isFloatTy() ||
- CDS->getElementType()->isDoubleTy())
- printConstant(CDS->getElementAsAPFloat(i), CS);
- else
- CS << "?";
- }
- }
- CS << "]";
- OutStreamer.AddComment(CS.str());
- } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
- int NumOperands = CV->getNumOperands();
- if ((BitWidth % CstEltSize) == 0)
- NumOperands = std::min<int>(NumOperands, BitWidth / CstEltSize);
- CS << "<";
- for (int l = 0; l != NumLanes; ++l) {
- for (int i = 0; i < NumOperands; ++i) {
- if (i != 0 || l != 0)
- CS << ",";
- printConstant(CV->getOperand(i),
- CV->getType()->getPrimitiveSizeInBits(), CS);
- }
- }
- CS << ">";
- OutStreamer.AddComment(CS.str());
- }
- }
-}
-
-static void printElementBroadcast(const MachineInstr *MI,
- MCStreamer &OutStreamer, int NumElts,
- int EltBits) {
+static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer,
+ int Repeats, int BitWidth) {
if (auto *C = X86::getConstantFromPool(*MI, 1)) {
std::string Comment;
raw_string_ostream CS(Comment);
const MachineOperand &DstOp = MI->getOperand(0);
CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
CS << "[";
- for (int i = 0; i != NumElts; ++i) {
- if (i != 0)
+ for (int l = 0; l != Repeats; ++l) {
+ if (l != 0)
CS << ",";
- printConstant(C, EltBits, CS);
+ printConstant(C, BitWidth, CS);
}
CS << "]";
OutStreamer.AddComment(CS.str());
@@ -1954,13 +1904,13 @@ static void addConstantComments(const MachineInstr *MI,
// For loads from a constant pool to a vector register, print the constant
// loaded.
CASE_128_MOV_RM()
- printLaneBroadcast(MI, OutStreamer, 1, 128);
+ printBroadcast(MI, OutStreamer, 1, 128);
break;
CASE_256_MOV_RM()
- printLaneBroadcast(MI, OutStreamer, 1, 256);
+ printBroadcast(MI, OutStreamer, 1, 256);
break;
CASE_512_MOV_RM()
- printLaneBroadcast(MI, OutStreamer, 1, 512);
+ printBroadcast(MI, OutStreamer, 1, 512);
break;
case X86::VBROADCASTF128rm:
case X86::VBROADCASTI128rm:
@@ -1968,19 +1918,19 @@ static void addConstantComments(const MachineInstr *MI,
case X86::VBROADCASTF64X2Z128rm:
case X86::VBROADCASTI32X4Z256rm:
case X86::VBROADCASTI64X2Z128rm:
- printLaneBroadcast(MI, OutStreamer, 2, 128);
+ printBroadcast(MI, OutStreamer, 2, 128);
break;
case X86::VBROADCASTF32X4rm:
case X86::VBROADCASTF64X2rm:
case X86::VBROADCASTI32X4rm:
case X86::VBROADCASTI64X2rm:
- printLaneBroadcast(MI, OutStreamer, 4, 128);
+ printBroadcast(MI, OutStreamer, 4, 128);
break;
case X86::VBROADCASTF32X8rm:
case X86::VBROADCASTF64X4rm:
case X86::VBROADCASTI32X8rm:
case X86::VBROADCASTI64X4rm:
- printLaneBroadcast(MI, OutStreamer, 2, 256);
+ printBroadcast(MI, OutStreamer, 2, 256);
break;
// For broadcast loads from a constant pool to a vector register, repeatedly
@@ -1990,55 +1940,55 @@ static void addConstantComments(const MachineInstr *MI,
case X86::VMOVDDUPZ128rm:
case X86::VPBROADCASTQrm:
case X86::VPBROADCASTQZ128rm:
- printElementBroadcast(MI, OutStreamer, 2, 64);
+ printBroadcast(MI, OutStreamer, 2, 64);
break;
case X86::VBROADCASTSDYrm:
case X86::VBROADCASTSDZ256rm:
case X86::VPBROADCASTQYrm:
case X86::VPBROADCASTQZ256rm:
- printElementBroadcast(MI, OutStreamer, 4, 64);
+ printBroadcast(MI, OutStreamer, 4, 64);
break;
case X86::VBROADCASTSDZrm:
case X86::VPBROADCASTQZrm:
- printElementBroadcast(MI, OutStreamer, 8, 64);
+ printBroadcast(MI, OutStreamer, 8, 64);
break;
case X86::VBROADCASTSSrm:
case X86::VBROADCASTSSZ128rm:
case X86::VPBROADCASTDrm:
case X86::VPBROADCASTDZ128rm:
- printElementBroadcast(MI, OutStreamer, 4, 32);
+ printBroadcast(MI, OutStreamer, 4, 32);
break;
case X86::VBROADCASTSSYrm:
case X86::VBROADCASTSSZ256rm:
case X86::VPBROADCASTDYrm:
case X86::VPBROADCASTDZ256rm:
- printElementBroadcast(MI, OutStreamer, 8, 32);
+ printBroadcast(MI, OutStreamer, 8, 32);
break;
case X86::VBROADCASTSSZrm:
case X86::VPBROADCASTDZrm:
- printElementBroadcast(MI, OutStreamer, 16, 32);
+ printBroadcast(MI, OutStreamer, 16, 32);
break;
case X86::VPBROADCASTWrm:
case X86::VPBROADCASTWZ128rm:
- printElementBroadcast(MI, OutStreamer, 8, 16);
+ printBroadcast(MI, OutStreamer, 8, 16);
break;
case X86::VPBROADCASTWYrm:
case X86::VPBROADCASTWZ256rm:
- printElementBroadcast(MI, OutStreamer, 16, 16);
+ printBroadcast(MI, OutStreamer, 16, 16);
break;
case X86::VPBROADCASTWZrm:
- printElementBroadcast(MI, OutStreamer, 32, 16);
+ printBroadcast(MI, OutStreamer, 32, 16);
break;
case X86::VPBROADCASTBrm:
case X86::VPBROADCASTBZ128rm:
- printElementBroadcast(MI, OutStreamer, 16, 8);
+ printBroadcast(MI, OutStreamer, 16, 8);
break;
case X86::VPBROADCASTBYrm:
case X86::VPBROADCASTBZ256rm:
- printElementBroadcast(MI, OutStreamer, 32, 8);
+ printBroadcast(MI, OutStreamer, 32, 8);
break;
case X86::VPBROADCASTBZrm:
- printElementBroadcast(MI, OutStreamer, 64, 8);
+ printBroadcast(MI, OutStreamer, 64, 8);
break;
}
}
diff --git a/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll b/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
index dd8efe9715d3af..b5577c09c43207 100644
--- a/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
+++ b/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
@@ -16,7 +16,7 @@ define fastcc double @tailcall() {
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fld1
; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
-; CHECK-NEXT: movaps {{.*#+}} xmm0 = <1.0E+0,1.0E+0,u,u>
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,1.0E+0,u,u]
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: jmp _tailcallee ## TAILCALL
entry:
diff --git a/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll b/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll
index 171e16e35fc2f0..5a4cbac57eeebb 100644
--- a/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll
+++ b/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll
@@ -73,7 +73,7 @@ define void @full_test() {
; X86-NEXT: cvtdq2ps %xmm0, %xmm1
; X86-NEXT: xorps %xmm0, %xmm0
; X86-NEXT: cmpltps %xmm2, %xmm0
-; X86-NEXT: movaps {{.*#+}} xmm3 = <1.0E+0,1.0E+0,u,u>
+; X86-NEXT: movaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,u,u]
; X86-NEXT: addps %xmm1, %xmm3
; X86-NEXT: movaps %xmm1, %xmm4
; X86-NEXT: blendvps %xmm0, %xmm3, %xmm4
@@ -93,7 +93,7 @@ define void @full_test() {
; X64-NEXT: cvtdq2ps %xmm0, %xmm1
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: cmpltps %xmm2, %xmm0
-; X64-NEXT: movaps {{.*#+}} xmm3 = <1.0E+0,1.0E+0,u,u>
+; X64-NEXT: movaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,u,u]
; X64-NEXT: addps %xmm1, %xmm3
; X64-NEXT: movaps %xmm1, %xmm4
; X64-NEXT: blendvps %xmm0, %xmm3, %xmm4
diff --git a/llvm/test/CodeGen/X86/addsub-constant-folding.ll b/llvm/test/CodeGen/X86/addsub-constant-folding.ll
index 4dbaae5c1a74ae..1cdc81223168f0 100644
--- a/llvm/test/CodeGen/X86/addsub-constant-folding.ll
+++ b/llvm/test/CodeGen/X86/addsub-constant-folding.ll
@@ -367,14 +367,14 @@ define <4 x i32> @vec_add_const_const_sub_extrause(<4 x i32> %arg) {
define <4 x i32> @vec_add_const_const_sub_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_add_const_const_sub_nonsplat:
; X86: # %bb.0:
-; X86-NEXT: movdqa {{.*#+}} xmm1 = <4294967277,u,u,4294967290>
+; X86-NEXT: movdqa {{.*#+}} xmm1 = [4294967277,u,u,4294967290]
; X86-NEXT: psubd %xmm0, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: vec_add_const_const_sub_nonsplat:
; X64: # %bb.0:
-; X64-NEXT: movdqa {{.*#+}} xmm1 = <4294967277,u,u,4294967290>
+; X64-NEXT: movdqa {{.*#+}} xmm1 = [4294967277,u,u,4294967290]
; X64-NEXT: psubd %xmm0, %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq
@@ -733,14 +733,14 @@ define <4 x i32> @vec_sub_const_const_sub_extrause(<4 x i32> %arg) {
define <4 x i32> @vec_sub_const_const_sub_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_sub_const_const_sub_nonsplat:
; X86: # %bb.0:
-; X86-NEXT: movdqa {{.*#+}} xmm1 = <23,u,u,10>
+; X86-NEXT: movdqa {{.*#+}} xmm1 = [23,u,u,10]
; X86-NEXT: psubd %xmm0, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: vec_sub_const_const_sub_nonsplat:
; X64: # %bb.0:
-; X64-NEXT: movdqa {{.*#+}} xmm1 = <23,u,u,10>
+; X64-NEXT: movdqa {{.*#+}} xmm1 = [23,u,u,10]
; X64-NEXT: psubd %xmm0, %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq
@@ -867,14 +867,14 @@ define <4 x i32> @vec_const_sub_add_const_extrause(<4 x i32> %arg) {
define <4 x i32> @vec_const_sub_add_const_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_const_sub_add_const_nonsplat:
; X86: # %bb.0:
-; X86-NEXT: movdqa {{.*#+}} xmm1 = <23,u,u,10>
+; X86-NEXT: movdqa {{.*#+}} xmm1 = [23,u,u,10]
; X86-NEXT: psubd %xmm0, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: vec_const_sub_add_const_nonsplat:
; X64: # %bb.0:
-; X64-NEXT: movdqa {{.*#+}} xmm1 = <23,u,u,10>
+; X64-NEXT: movdqa {{.*#+}} xmm1 = [23,u,u,10]
; X64-NEXT: psubd %xmm0, %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq
@@ -1001,14 +1001,14 @@ define <4 x i32> @vec_const_sub_sub_const_extrause(<4 x i32> %arg) {
define <4 x i32> @vec_const_sub_sub_const_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_const_sub_sub_const_nonsplat:
; X86: # %bb.0:
-; X86-NEXT: movdqa {{.*#+}} xmm1 = <19,u,u,6>
+; X86-NEXT: movdqa {{.*#+}} xmm1 = [19,u,u,6]
; X86-NEXT: psubd %xmm0, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: vec_const_sub_sub_const_nonsplat:
; X64: # %bb.0:
-; X64-NEXT: movdqa {{.*#+}} xmm1 = <19,u,u,6>
+; X64-NEXT: movdqa {{.*#+}} xmm1 = [19,u,u,6]
; X64-NEXT: psubd %xmm0, %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll b/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
index d61e33ccb22a95..fe48059f9d0e65 100644
--- a/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
+++ b/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
@@ -1053,7 +1053,7 @@ define void @vec256_i8_widen_to_i16_factor2_broadcast_to_v16i16_factor16(ptr %in
; SSE42-NEXT: paddb 48(%rsi), %xmm2
; SSE42-NEXT: paddb (%rsi), %xmm0
; SSE42-NEXT: paddb 32(%rsi), %xmm1
-; SSE42-NEXT: movdqa {{.*#+}} xmm3 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u>
+; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u]
; SSE42-NEXT: pshufb %xmm3, %xmm1
; SSE42-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE42-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
@@ -3941,7 +3941,7 @@ define void @vec384_i16_widen_to_i96_factor6_broadcast_to_v4i96_factor4(ptr %in.
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpaddb (%rsi), %zmm0, %zmm0
; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = <16,9,10,11,12,13,16,15,u,u,u,u,16,u,u,u>
+; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [16,9,10,11,12,13,16,15,u,u,u,u,16,u,u,u]
; AVX512BW-NEXT: vpermi2w %ymm0, %ymm1, %ymm2
; AVX512BW-NEXT: vpbroadcastw %xmm0, %ymm0
; AVX512BW-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0
@@ -4181,7 +4181,7 @@ define void @vec384_i16_widen_to_i192_factor12_broadcast_to_v2i192_factor2(ptr %
; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0
; AVX512BW-NEXT: vpaddb (%rsi), %zmm0, %zmm0
; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = <16,9,10,11,12,13,14,15,u,u,u,u,16,u,u,u>
+; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [16,9,10,11,12,13,14,15,u,u,u,u,16,u,u,u]
; AVX512BW-NEXT: vpermi2w %ymm0, %ymm1, %ymm2
; AVX512BW-NEXT: vpaddb (%rdx), %zmm2, %zmm0
; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rcx)
diff --git a/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll b/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
index 99d9f6b41e70dd..2f576fe6715904 100644
--- a/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
+++ b/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
@@ -875,7 +875,7 @@ define void @vec256_i8_widen_to_i16_factor2_broadcast_to_v16i16_factor16(ptr %in
; SSE42-NEXT: movdqa (%rdi), %xmm0
; SSE42-NEXT: movdqa 32(%rdi), %xmm1
; SSE42-NEXT: movdqa 48(%rdi), %xmm2
-; SSE42-NEXT: movdqa {{.*#+}} xmm3 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u>
+; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u]
; SSE42-NEXT: pshufb %xmm3, %xmm1
; SSE42-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE42-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
diff --git a/llvm/test/CodeGen/X86/avx2-fma-fneg-combine.ll b/llvm/test/CodeGen/X86/avx2-fma-fneg-combine.ll
index d6001da849e31f..ee504e30302b13 100644
--- a/llvm/test/CodeGen/X86/avx2-fma-fneg-combine.ll
+++ b/llvm/test/CodeGen/X86/avx2-fma-fneg-combine.ll
@@ -131,7 +131,7 @@ define <4 x double> @test9(<4 x double> %a) {
define <4 x double> @test10(<4 x double> %a, <4 x double> %b) {
; CHECK-LABEL: test10:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} ymm2 = <-9.5E+0,u,-5.5E+0,-2.5E+0>
+; CHECK-NEXT: vmovapd {{.*#+}} ymm2 = [-9.5E+0,u,-5.5E+0,-2.5E+0]
; CHECK-NEXT: vmovapd %ymm2, %ymm3
; CHECK-NEXT: vfmadd213pd {{.*#+}} ymm3 = (ymm0 * ymm3) + ymm1
; CHECK-NEXT: vfnmadd213pd {{.*#+}} ymm2 = -(ymm0 * ymm2) + ymm1
diff --git a/llvm/test/CodeGen/X86/avx2-vperm.ll b/llvm/test/CodeGen/X86/avx2-vperm.ll
index 101fd193127880..90430aa51dcdc0 100644
--- a/llvm/test/CodeGen/X86/avx2-vperm.ll
+++ b/llvm/test/CodeGen/X86/avx2-vperm.ll
@@ -23,13 +23,13 @@ entry:
define <8 x float> @perm_cl_fp_8x32(<8 x float> %A) nounwind readnone {
; X86-LABEL: perm_cl_fp_8x32:
; X86: # %bb.0: # %entry
-; X86-NEXT: vmovaps {{.*#+}} ymm1 = <u,7,2,u,4,u,1,6>
+; X86-NEXT: vmovaps {{.*#+}} ymm1 = [u,7,2,u,4,u,1,6]
; X86-NEXT: vpermps %ymm0, %ymm1, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: perm_cl_fp_8x32:
; X64: # %bb.0: # %entry
-; X64-NEXT: vmovaps {{.*#+}} ymm1 = <u,7,2,u,4,u,1,6>
+; X64-NEXT: vmovaps {{.*#+}} ymm1 = [u,7,2,u,4,u,1,6]
; X64-NEXT: vpermps %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll b/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
index ec0f14ae4e58e3..b648b086a8b689 100644
--- a/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
+++ b/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
@@ -1769,7 +1769,7 @@ define <4 x i32> @test_16xi32_to_4xi32_perm_mask9(<16 x i32> %vec) {
;
; CHECK-FAST-PERLANE-LABEL: test_16xi32_to_4xi32_perm_mask9:
; CHECK-FAST-PERLANE: # %bb.0:
-; CHECK-FAST-PERLANE-NEXT: vmovdqa {{.*#+}} xmm1 = <4,1,u,2>
+; CHECK-FAST-PERLANE-NEXT: vmovdqa {{.*#+}} xmm1 = [4,1,u,2]
; CHECK-FAST-PERLANE-NEXT: vextracti64x4 $1, %zmm0, %ymm2
; CHECK-FAST-PERLANE-NEXT: vpermd %ymm2, %ymm1, %ymm1
; CHECK-FAST-PERLANE-NEXT: vextracti128 $1, %ymm0, %xmm2
diff --git a/llvm/test/CodeGen/X86/bitreverse.ll b/llvm/test/CodeGen/X86/bitreverse.ll
index 9daac1df1d9750..2d978b5e991c91 100644
--- a/llvm/test/CodeGen/X86/bitreverse.ll
+++ b/llvm/test/CodeGen/X86/bitreverse.ll
@@ -587,7 +587,7 @@ define <2 x i16> @fold_v2i16() {
;
; X64-LABEL: fold_v2i16:
; X64: # %bb.0:
-; X64-NEXT: movaps {{.*#+}} xmm0 = <61440,240,u,u,u,u,u,u>
+; X64-NEXT: movaps {{.*#+}} xmm0 = [61440,240,u,u,u,u,u,u]
; X64-NEXT: retq
;
; X86XOP-LABEL: fold_v2i16:
diff --git a/llvm/test/CodeGen/X86/combine-sdiv.ll b/llvm/test/CodeGen/X86/combine-sdiv.ll
index 549fe726269730..e10d94c16696a2 100644
--- a/llvm/test/CodeGen/X86/combine-sdiv.ll
+++ b/llvm/test/CodeGen/X86/combine-sdiv.ll
@@ -581,7 +581,7 @@ define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: psraw $15, %xmm0
-; SSE2-NEXT: movdqa {{.*#+}} xmm7 = <u,4,2,16,8,32,64,2>
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [u,4,2,16,8,32,64,2]
; SSE2-NEXT: pmulhuw %xmm7, %xmm0
; SSE2-NEXT: paddw %xmm3, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [65535,65535,65535,0,65535,0,0,65535]
@@ -639,10 +639,10 @@ define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) {
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: psraw $15, %xmm2
-; SSE41-NEXT: movdqa {{.*#+}} xmm3 = <u,4,2,16,8,32,64,2>
+; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [u,4,2,16,8,32,64,2]
; SSE41-NEXT: pmulhuw %xmm3, %xmm2
; SSE41-NEXT: paddw %xmm0, %xmm2
-; SSE41-NEXT: movdqa {{.*#+}} xmm4 = <u,16384,32768,4096,8192,2048,1024,32768>
+; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [u,16384,32768,4096,8192,2048,1024,32768]
; SSE41-NEXT: movdqa %xmm2, %xmm5
; SSE41-NEXT: pmulhw %xmm4, %xmm5
; SSE41-NEXT: psraw $1, %xmm2
@@ -662,10 +662,10 @@ define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) {
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpsraw $15, %xmm1, %xmm2
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = <u,4,2,16,8,32,64,2>
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [u,4,2,16,8,32,64,2]
; AVX1-NEXT: vpmulhuw %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpaddw %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <u,16384,32768,4096,8192,2048,1024,32768>
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [u,16384,32768,4096,8192,2048,1024,32768]
; AVX1-NEXT: vpmulhw %xmm2, %xmm1, %xmm4
; AVX1-NEXT: vpsraw $1, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm4[0,1],xmm1[2],xmm4[3,4,5,6],xmm1[7]
@@ -718,10 +718,10 @@ define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) {
; XOP: # %bb.0:
; XOP-NEXT: vextractf128 $1, %ymm0, %xmm1
; XOP-NEXT: vpsraw $15, %xmm1, %xmm2
-; XOP-NEXT: vmovdqa {{.*#+}} xmm3 = <u,65522,65521,65524,65523,65525,65526,65521>
+; XOP-NEXT: vmovdqa {{.*#+}} xmm3 = [u,65522,65521,65524,65523,65525,65526,65521]
; XOP-NEXT: vpshlw %xmm3, %xmm2, %xmm2
; XOP-NEXT: vpaddw %xmm2, %xmm1, %xmm1
-; XOP-NEXT: vmovdqa {{.*#+}} xmm2 = <u,65534,65535,65532,65533,65531,65530,65535>
+; XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [u,65534,65535,65532,65533,65531,65530,65535]
; XOP-NEXT: vpshaw %xmm2, %xmm1, %xmm1
; XOP-NEXT: vpsraw $15, %xmm0, %xmm4
; XOP-NEXT: vpshlw %xmm3, %xmm4, %x...
[truncated]
|
This is /almost/ NFC - the only annoyance is that for some reason we were using "<C1,C2,..>" for ConstantVector types unlike all other cases - these now use the same "[C1,C2,..]" format as the other constant printers. I don't think we have any reason to keep this diff, but I'm putting up this PR just in case there's a reason I've forgotten.
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This is /almost/ NFC - the only annoyance is that for some reason we were using "<C1,C2,..>" for ConstantVector types unlike all other cases - these now use the same "[C1,C2,..]" format as the other constant printers.
I don't think we have any reason to keep this diff, but I'm putting up this PR just in case there's a reason I've forgotten.