[InstCombine] Precommit test for #79417. NFC.

[bzEq]

No description provided.

[llvmbot]

@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-backend-x86

Author: Kai Luo (bzEq)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/79418.diff

4 Files Affected:

• (added) llvm/test/CodeGen/AArch64/absdiff.ll (+18)
• (added) llvm/test/CodeGen/PowerPC/absdiff.ll (+19)
• (added) llvm/test/CodeGen/X86/absdiff.ll (+22)
• (added) llvm/test/Transforms/InstCombine/sub-xor-cmp.ll (+20)

diff --git a/llvm/test/CodeGen/AArch64/absdiff.ll b/llvm/test/CodeGen/AArch64/absdiff.ll
new file mode 100644
index 000000000000000..ca7b5a583cbe51e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/absdiff.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -mtriple=aarch64-linux-gnu -passes=instcombine < %s -o - | llc -mtriple=aarch64-linux-gnu -o - | FileCheck %s
+
+define  i64 @absdiff(i64 %0, i64 %1) {
+; CHECK-LABEL: absdiff:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    subs x8, x0, x1
+; CHECK-NEXT:    csetm x9, lo
+; CHECK-NEXT:    cinv x8, x8, lo
+; CHECK-NEXT:    sub x0, x8, x9
+; CHECK-NEXT:    ret
+  %3 = icmp ult i64 %0, %1
+  %4 = sext i1 %3 to i64
+  %5 = sub i64 %0, %1
+  %6 = xor i64 %5, %4
+  %7 = sub i64 %6, %4
+  ret i64 %7
+}
diff --git a/llvm/test/CodeGen/PowerPC/absdiff.ll b/llvm/test/CodeGen/PowerPC/absdiff.ll
new file mode 100644
index 000000000000000..a26482fc6497b8a
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/absdiff.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -mtriple=powerpc64-linux-gnu -passes=instcombine < %s -o - | llc -mtriple=powerpc64-linux-gnu -o - | FileCheck %s
+
+define  i64 @absdiff(i64 %0, i64 %1) {
+; CHECK-LABEL: absdiff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subc 5, 3, 4
+; CHECK-NEXT:    subfe 5, 3, 3
+; CHECK-NEXT:    sub 3, 3, 4
+; CHECK-NEXT:    xor 3, 3, 5
+; CHECK-NEXT:    sub 3, 3, 5
+; CHECK-NEXT:    blr
+  %3 = icmp ult i64 %0, %1
+  %4 = sext i1 %3 to i64
+  %5 = sub i64 %0, %1
+  %6 = xor i64 %5, %4
+  %7 = sub i64 %6, %4
+  ret i64 %7
+}
diff --git a/llvm/test/CodeGen/X86/absdiff.ll b/llvm/test/CodeGen/X86/absdiff.ll
new file mode 100644
index 000000000000000..46c7b62e43685b7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/absdiff.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -mtriple=x86_64-linux-gnu -passes=instcombine < %s -o - | llc -mtriple=x86_64-linux-gnu -o - | FileCheck %s
+
+define  i64 @absdiff(i64 %0, i64 %1) {
+; CHECK-LABEL: absdiff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    movq %rdi, %rcx
+; CHECK-NEXT:    subq %rsi, %rcx
+; CHECK-NEXT:    setb %al
+; CHECK-NEXT:    negq %rax
+; CHECK-NEXT:    xorq %rcx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    adcq $0, %rax
+; CHECK-NEXT:    retq
+  %3 = icmp ult i64 %0, %1
+  %4 = sext i1 %3 to i64
+  %5 = sub i64 %0, %1
+  %6 = xor i64 %5, %4
+  %7 = sub i64 %6, %4
+  ret i64 %7
+}
diff --git a/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll b/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll
new file mode 100644
index 000000000000000..0555bc1c365f5a4
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/sub-xor-cmp.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define  i64 @absdiff(i64 %0, i64 %1) {
+; CHECK-LABEL: define i64 @absdiff(
+; CHECK-SAME: i64 [[TMP0:%.*]], i64 [[TMP1:%.*]]) {
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp ult i64 [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = sext i1 [[TMP3]] to i64
+; CHECK-NEXT:    [[TMP5:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP6:%.*]] = xor i64 [[TMP5]], [[TMP4]]
+; CHECK-NEXT:    [[TMP7:%.*]] = sub i64 [[TMP6]], [[TMP4]]
+; CHECK-NEXT:    ret i64 [[TMP7]]
+;
+  %3 = icmp ult i64 %0, %1
+  %4 = sext i1 %3 to i64
+  %5 = sub i64 %0, %1
+  %6 = xor i64 %5, %4
+  %7 = sub i64 %6, %4
+  ret i64 %7
+}

[ecnelises]

Will the combination differ by triple? If this is opt change, I don't think we should mix opt runlines in codegen test to 'prove' combine result is better.

[RKSimon]

Please don't put instcombine tests in codegen

[bzEq]

Put codegen comparison in #79417 .

[ecnelises]

If this IR sequence doesn't change after instcombine currently, you can just add it in the patch. Also, maybe you can put it in files like abs-1.ll or abs_abs.ll.

[bzEq]

Put tests directly in #79417.