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[LoongArch] Fixing the incorrect return value of LoongArchTTIImpl::getRegisterBitWidth #79441

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merged 2 commits into from
Jan 26, 2024

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@wangleiat wangleiat commented Jan 25, 2024

When we do not enable vector features, we should return the default value (TargetTransformInfoImplBase::getRegisterBitWidth) instead of zero.

This should fix the LoongArch buildbot breakage from #78943.

…tRegisterBitWidth

When we do not enable vector features, we should return the default
value (TargetTransformInfoImplBase::getRegisterBitWidth) instead of
zero.

This should fix the LoongArch buildbot breakage from llvm#78943.
https://lab.llvm.org/staging/#/builders/5
@llvmbot
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llvmbot commented Jan 25, 2024

@llvm/pr-subscribers-backend-loongarch

Author: wanglei (wangleiat)

Changes

When we do not enable vector features, we should return the default value (TargetTransformInfoImplBase::getRegisterBitWidth) instead of zero.

This should fix the LoongArch buildbot breakage from #78943.
https://lab.llvm.org/staging/#/builders/5


Full diff: https://github.com/llvm/llvm-project/pull/79441.diff

1 Files Affected:

  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp (+7-4)
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
index 04349aa52b54089..d47dded9ea6ecf2 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
@@ -21,17 +21,20 @@ using namespace llvm;
 
 TypeSize LoongArchTTIImpl::getRegisterBitWidth(
     TargetTransformInfo::RegisterKind K) const {
+  TypeSize DefSize = TargetTransformInfoImplBase::getRegisterBitWidth(K);
   switch (K) {
   case TargetTransformInfo::RGK_Scalar:
     return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
   case TargetTransformInfo::RGK_FixedWidthVector:
-    if (ST->hasExtLASX() && ST->hasExpAutoVec())
+    if (!ST->hasExpAutoVec())
+      return DefSize;
+    if (ST->hasExtLASX())
       return TypeSize::getFixed(256);
-    if (ST->hasExtLSX() && ST->hasExpAutoVec())
+    if (ST->hasExtLSX())
       return TypeSize::getFixed(128);
-    return TypeSize::getFixed(0);
+    [[fallthrough]];
   case TargetTransformInfo::RGK_ScalableVector:
-    return TypeSize::getScalable(0);
+    return DefSize;
   }
 
   llvm_unreachable("Unsupported register kind");

@wangleiat wangleiat merged commit 1e9924c into llvm:main Jan 26, 2024
3 of 4 checks passed
llvmbot pushed a commit to llvmbot/llvm-project that referenced this pull request Feb 4, 2024
…tRegisterBitWidth (llvm#79441)

When we do not enable vector features, we should return the default
value (`TargetTransformInfoImplBase::getRegisterBitWidth`) instead of
zero.

This should fix the LoongArch [buildbot
breakage](https://lab.llvm.org/staging/#/builders/5/builds/486) from
llvm#78943.

(cherry picked from commit 1e9924c)
llvmbot pushed a commit to llvmbot/llvm-project that referenced this pull request Feb 4, 2024
…tRegisterBitWidth (llvm#79441)

When we do not enable vector features, we should return the default
value (`TargetTransformInfoImplBase::getRegisterBitWidth`) instead of
zero.

This should fix the LoongArch [buildbot
breakage](https://lab.llvm.org/staging/#/builders/5/builds/486) from
llvm#78943.

(cherry picked from commit 1e9924c)
tstellar pushed a commit to tstellar/llvm-project that referenced this pull request Feb 14, 2024
…tRegisterBitWidth (llvm#79441)

When we do not enable vector features, we should return the default
value (`TargetTransformInfoImplBase::getRegisterBitWidth`) instead of
zero.

This should fix the LoongArch [buildbot
breakage](https://lab.llvm.org/staging/#/builders/5/builds/486) from
llvm#78943.

(cherry picked from commit 1e9924c)
tstellar pushed a commit to tstellar/llvm-project that referenced this pull request Feb 14, 2024
…tRegisterBitWidth (llvm#79441)

When we do not enable vector features, we should return the default
value (`TargetTransformInfoImplBase::getRegisterBitWidth`) instead of
zero.

This should fix the LoongArch [buildbot
breakage](https://lab.llvm.org/staging/#/builders/5/builds/486) from
llvm#78943.

(cherry picked from commit 1e9924c)
tstellar pushed a commit to tstellar/llvm-project that referenced this pull request Feb 14, 2024
…tRegisterBitWidth (llvm#79441)

When we do not enable vector features, we should return the default
value (`TargetTransformInfoImplBase::getRegisterBitWidth`) instead of
zero.

This should fix the LoongArch [buildbot
breakage](https://lab.llvm.org/staging/#/builders/5/builds/486) from
llvm#78943.

(cherry picked from commit 1e9924c)
tstellar pushed a commit to tstellar/llvm-project that referenced this pull request Feb 14, 2024
…tRegisterBitWidth (llvm#79441)

When we do not enable vector features, we should return the default
value (`TargetTransformInfoImplBase::getRegisterBitWidth`) instead of
zero.

This should fix the LoongArch [buildbot
breakage](https://lab.llvm.org/staging/#/builders/5/builds/486) from
llvm#78943.

(cherry picked from commit 1e9924c)
@wangleiat wangleiat deleted the dev branch March 4, 2024 03:10
@pointhex pointhex mentioned this pull request May 7, 2024
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3 participants