[CodeGen] Don't include aliases in RegisterClassInfo::IgnoreCSRForAllocOrder

[jayfoad]

Previously we called ignoreCSRForAllocationOrder on every alias of every
CSR which was expensive on targets like AMDGPU which define a very large
number of overlapping register tuples.

On such targets it is simpler and faster to call
ignoreCSRForAllocationOrder once for every physical register.

Differential Revision: https://reviews.llvm.org/D146735

[llvmbot]

@llvm/pr-subscribers-llvm-regalloc

Author: Jay Foad (jayfoad)

Changes

Previously we called ignoreCSRForAllocationOrder on every alias of every
CSR which was expensive on targets like AMDGPU which define a very large
number of overlapping register tuples.

On such targets it is simpler and faster to call
ignoreCSRForAllocationOrder once for every physical register.

Differential Revision: https://reviews.llvm.org/D146735

---

Full diff: https://github.com/llvm/llvm-project/pull/80015.diff

1 Files Affected:

• (modified) llvm/lib/CodeGen/RegisterClassInfo.cpp (+3-5)

diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 8869a861de06..1dd595bc140c 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -93,11 +93,9 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
   // Even if CSR list is same, we could have had a different allocation order
   // if ignoreCSRForAllocationOrder is evaluated differently.
   BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
-  for (const MCPhysReg *I = CSR; *I; ++I)
-    for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
-      CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
-  if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
-      IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
+  for (MCPhysReg I = 1, E = TRI->getNumRegs(); I != E; ++I)
+    CSRHintsForAllocOrder[I] = STI.ignoreCSRForAllocationOrder(mf, I);
+  if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
     Update = true;
     IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
   }

[jayfoad]

Migrated from Phabricator. There is some discussion there: https://reviews.llvm.org/D146735

[nikic]

It looks like this approach is faster on AMDGPU, but slower on more conventional architectures: http://llvm-compile-time-tracker.com/compare.php?from=db49319264d6d2b6f9f7b345495d543210c2cfe3&to=f8525030004f907cd108e7c18df255a6d3b23124&stat=instructions:u

[jayfoad]

It looks like this approach is faster on AMDGPU, but slower on more conventional architectures:

Thanks for keeping me honest! I will revert and rethink.