[RISCV] Register fixed stack slots for callee saved registers for -ms… #81392
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…ave-restore/Zcmp. PEI previously used fake frame indices for these callee saved registers. These fake frame indices are not register with MachineFrameInfo. This required them to be deleted form CalleeSavedInfo after PEI to avoid breaking later passes. See llvm#79535 Unfortunately, removing the registers from CalleeSavedInfo pessimizes Interprocedural Register Allocation. The RegUsageInfoCollector pass runs after PEI and uses CalleeSavedInfo. This patch replaces llvm#79535 by properly creating fixed stack objects through MachineFrameInfo. This changes the stack size and offsets returned by MachineFrameInfo which requires changes to how RISCVFrameLowering uses that information. In addition to the individual object for each register, I've also create a single large fixed object that covers the entire stack area covered by cm.push or the libcalls. cm.push must always push a multiple of 16 bytes and the save restore libcall pushes a multiple of stack align. I think this leaves holes in the stack where we could spill other registers, but it matches what we did previously. Maybe we can optimize this in the future. The only test changes are due to stack alignment handling after the callee save registers. Since we now have the fixed objects, on the stack the offset is non-zero when an aligned object is processed so the offset gets rounded up, increasing the stack size.
topperc
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) Changes…ave-restore/Zcmp. PEI previously used fake frame indices for these callee saved registers. These fake frame indices are not register with MachineFrameInfo. This required them to be deleted form CalleeSavedInfo after PEI to avoid breaking later passes. See #79535 Unfortunately, removing the registers from CalleeSavedInfo pessimizes Interprocedural Register Allocation. The RegUsageInfoCollector pass runs after PEI and uses CalleeSavedInfo. This patch replaces #79535 by properly creating fixed stack objects through MachineFrameInfo. This changes the stack size and offsets returned by MachineFrameInfo which requires changes to how RISCVFrameLowering uses that information. In addition to the individual object for each register, I've also create a single large fixed object that covers the entire stack area covered by cm.push or the libcalls. cm.push must always push a multiple of 16 bytes and the save restore libcall pushes a multiple of stack align. I think this leaves holes in the stack where we could spill other registers, but it matches what we did previously. Maybe we can optimize this in the future. The only test changes are due to stack alignment handling after the callee save registers. Since we now have the fixed objects, on the stack the offset is non-zero when an aligned object is processed so the offset gets rounded up, increasing the stack size. I suspect we might need some more updates for RVV related code. There is very little or maybe even no testing of RVV mixed with Zcmp and save-restore. Patch is 28.13 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/81392.diff 5 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 37672dd047f2d..01b73cc761cca 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -291,9 +291,7 @@ static Register getMaxPushPopReg(const MachineFunction &MF,
const std::vector<CalleeSavedInfo> &CSI) {
Register MaxPushPopReg = RISCV::NoRegister;
for (auto &CS : CSI) {
- // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indices to
- // registers which can be saved by Zcmp Push.
- if (CS.getFrameIdx() < 0)
+ if (llvm::is_contained(AllPopRegs, CS.getReg().id()))
MaxPushPopReg = std::max(MaxPushPopReg.id(), CS.getReg().id());
}
// if rlist is {rs, s0-s10}, then s11 will also be included
@@ -532,8 +530,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
// investigation. Get the number of bytes to allocate from the FrameInfo.
- uint64_t StackSize = getStackSizeWithRVVPadding(MF);
- uint64_t RealStackSize = StackSize + RVFI->getReservedSpillsSize();
+ uint64_t RealStackSize = getStackSizeWithRVVPadding(MF);
+ uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
uint64_t RVVStackSize = RVFI->getRVVStackSize();
// Early exit if there is no need to allocate on the stack
@@ -590,20 +588,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// directives.
for (const auto &Entry : CSI) {
int FrameIdx = Entry.getFrameIdx();
- int64_t Offset;
- // Offsets for objects with fixed locations (IE: those saved by libcall) are
- // simply calculated from the frame index.
- if (FrameIdx < 0) {
- if (RVFI->isPushable(MF)) {
- // Callee-saved register stored by Zcmp push is in reverse order.
- Offset = -(FrameIdx + RVFI->getRVPushRegs() + 1) *
- (int64_t)STI.getXLen() / 8;
- } else {
- Offset = FrameIdx * (int64_t)STI.getXLen() / 8;
- }
- } else {
- Offset = MFI.getObjectOffset(FrameIdx) - RVFI->getReservedSpillsSize();
- }
+ int64_t Offset = MFI.getObjectOffset(FrameIdx);
Register Reg = Entry.getReg();
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
@@ -746,8 +731,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
if (!CSI.empty())
LastFrameDestroy = std::prev(MBBI, CSI.size());
- uint64_t StackSize = getStackSizeWithRVVPadding(MF);
- uint64_t RealStackSize = StackSize + RVFI->getReservedSpillsSize();
+ uint64_t RealStackSize = getStackSizeWithRVVPadding(MF);
+ uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
uint64_t RVVStackSize = RVFI->getRVVStackSize();
@@ -897,8 +882,6 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
if (FrameReg == getFPReg(STI)) {
Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize());
- if (FI >= 0)
- Offset -= StackOffset::getFixed(RVFI->getReservedSpillsSize());
// When using FP to access scalable vector objects, we need to minus
// the frame size.
//
@@ -965,8 +948,7 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
if (MFI.isFixedObjectIndex(FI)) {
assert(!RI->hasStackRealignment(MF) &&
"Can't index across variable sized realign");
- Offset += StackOffset::get(getStackSizeWithRVVPadding(MF) +
- RVFI->getReservedSpillsSize(),
+ Offset += StackOffset::get(getStackSizeWithRVVPadding(MF),
RVFI->getRVVStackSize());
} else {
Offset += StackOffset::getFixed(MFI.getStackSize());
@@ -1260,30 +1242,6 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
RVFI->setCalleeSavedStackSize(Size);
}
-void RISCVFrameLowering::processFunctionBeforeFrameIndicesReplaced(
- MachineFunction &MF, RegScavenger *RS) const {
- // Remove CalleeSavedInfo for registers saved by Zcmp or save/restore
- // libcalls.
- MachineFrameInfo &MFI = MF.getFrameInfo();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
- if (!RVFI->isPushable(MF) && !RVFI->useSaveRestoreLibCalls(MF))
- return;
- const std::vector<CalleeSavedInfo> &CSIs = MFI.getCalleeSavedInfo();
- std::vector<CalleeSavedInfo> NewCSIs;
- for (const auto &CSI : CSIs) {
- // Skip CSRs that have fake a frame index.
- int ReservedFI = 0;
- if (TRI->hasReservedSpillSlot(MF, CSI.getReg(), ReservedFI)) {
- assert(CSI.getFrameIdx() == ReservedFI &&
- "Reserved CSR spill slot frame index mismatch in CSI");
- continue;
- }
- NewCSIs.push_back(CSI);
- }
- MFI.setCalleeSavedInfo(std::move(NewCSIs));
-}
-
// Not preserve stack space within prologue for outgoing variables when the
// function contains variable size objects or there are vector objects accessed
// by the frame pointer.
@@ -1403,6 +1361,93 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const {
return 0;
}
+// Frame indexes representing locations of CSRs which are given a fixed location
+// by save/restore libcalls or Zcmp Push/Pop.
+static const std::pair<unsigned, int> FixedCSRFIMap[] = {
+ {/*ra*/ RISCV::X1, -1}, {/*s0*/ RISCV::X8, -2},
+ {/*s1*/ RISCV::X9, -3}, {/*s2*/ RISCV::X18, -4},
+ {/*s3*/ RISCV::X19, -5}, {/*s4*/ RISCV::X20, -6},
+ {/*s5*/ RISCV::X21, -7}, {/*s6*/ RISCV::X22, -8},
+ {/*s7*/ RISCV::X23, -9}, {/*s8*/ RISCV::X24, -10},
+ {/*s9*/ RISCV::X25, -11}, {/*s10*/ RISCV::X26, -12},
+ {/*s11*/ RISCV::X27, -13}};
+
+bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
+ MachineFunction &MF, const TargetRegisterInfo *TRI,
+ std::vector<CalleeSavedInfo> &CSI, unsigned &MinCSFrameIndex,
+ unsigned &MaxCSFrameIndex) const {
+ // Early exit if no callee saved registers are modified!
+ if (CSI.empty())
+ return true;
+
+ auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+
+ if (RVFI->isPushable(MF)) {
+ // Determine how many GPRs we need to push and save it to RVFI.
+ Register MaxReg = getMaxPushPopReg(MF, CSI);
+ if (MaxReg != RISCV::NoRegister) {
+ auto [RegEnc, PushedRegNum] = getPushPopEncodingAndNum(MaxReg);
+ RVFI->setRVPushRegs(PushedRegNum);
+ RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));
+
+ // Use encoded number to represent registers to spill.
+ RVFI->setRVPushRlist(RegEnc);
+ }
+ }
+
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
+
+ for (auto &CS : CSI) {
+ unsigned Reg = CS.getReg();
+ const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
+ unsigned Size = RegInfo->getSpillSize(*RC);
+
+ // This might need a fixed stack slot.
+ if (RVFI->useSaveRestoreLibCalls(MF) || RVFI->isPushable(MF)) {
+ const auto *FII = llvm::find_if(
+ FixedCSRFIMap, [&](auto P) { return P.first == CS.getReg(); });
+ if (FII != std::end(FixedCSRFIMap)) {
+ int64_t Offset;
+ if (RVFI->isPushable(MF))
+ Offset = -((FII->second + RVFI->getRVPushRegs() + 1) * (int64_t)Size);
+ else
+ Offset = FII->second * (int64_t)Size;
+
+ int FrameIdx = MFI.CreateFixedSpillStackObject(Size, Offset);
+ assert(FrameIdx < 0);
+ CS.setFrameIdx(FrameIdx);
+ continue;
+ }
+ }
+
+ // Not a fixed slot.
+ Align Alignment = RegInfo->getSpillAlign(*RC);
+ // We may not be able to satisfy the desired alignment specification of
+ // the TargetRegisterClass if the stack alignment is smaller. Use the
+ // min.
+ Alignment = std::min(Alignment, getStackAlign());
+ int FrameIdx = MFI.CreateStackObject(Size, Alignment, true);
+ if ((unsigned)FrameIdx < MinCSFrameIndex)
+ MinCSFrameIndex = FrameIdx;
+ if ((unsigned)FrameIdx > MaxCSFrameIndex)
+ MaxCSFrameIndex = FrameIdx;
+ CS.setFrameIdx(FrameIdx);
+ }
+
+ // Allocate a fixed object that covers the full push or libcall size.
+ if (RVFI->isPushable(MF)) {
+ if (int64_t PushSize = RVFI->getRVPushStackSize())
+ MFI.CreateFixedSpillStackObject(PushSize, -PushSize);
+ } else if (int LibCallRegs = getLibCallID(MF, CSI) + 1) {
+ int64_t LibCallFrameSize =
+ alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign());
+ MFI.CreateFixedSpillStackObject(LibCallFrameSize, -LibCallFrameSize);
+ }
+
+ return true;
+}
+
bool RISCVFrameLowering::spillCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
@@ -1418,14 +1463,10 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
// Emit CM.PUSH with base SPimm & evaluate Push stack
RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
if (RVFI->isPushable(*MF)) {
- Register MaxReg = getMaxPushPopReg(*MF, CSI);
- if (MaxReg != RISCV::NoRegister) {
- auto [RegEnc, PushedRegNum] = getPushPopEncodingAndNum(MaxReg);
- RVFI->setRVPushRegs(PushedRegNum);
- RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));
-
+ unsigned PushedRegNum = RVFI->getRVPushRegs();
+ if (PushedRegNum > 0) {
// Use encoded number to represent registers to spill.
- RVFI->setRVPushRlist(RegEnc);
+ int RegEnc = RVFI->getRVPushRlist();
MachineInstrBuilder PushBuilder =
BuildMI(MBB, MI, DL, TII.get(RISCV::CM_PUSH))
.setMIFlag(MachineInstr::FrameSetup);
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
index a784479f111b1..210f8c1064724 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
@@ -37,10 +37,6 @@ class RISCVFrameLowering : public TargetFrameLowering {
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS) const override;
- void
- processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF,
- RegScavenger *RS) const override;
-
bool hasFP(const MachineFunction &MF) const override;
bool hasBP(const MachineFunction &MF) const;
@@ -49,6 +45,12 @@ class RISCVFrameLowering : public TargetFrameLowering {
MachineBasicBlock::iterator
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;
+
+ bool assignCalleeSavedSpillSlots(MachineFunction &MF,
+ const TargetRegisterInfo *TRI,
+ std::vector<CalleeSavedInfo> &CSI,
+ unsigned &MinCSFrameIndex,
+ unsigned &MaxCSFrameIndex) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
ArrayRef<CalleeSavedInfo> CSI,
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 30457f528853b..ca519dbc4c035 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -156,40 +156,6 @@ const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
return CSR_NoRegs_RegMask;
}
-// Frame indexes representing locations of CSRs which are given a fixed location
-// by save/restore libcalls or Zcmp Push/Pop.
-static const std::pair<unsigned, int> FixedCSRFIMap[] = {
- {/*ra*/ RISCV::X1, -1},
- {/*s0*/ RISCV::X8, -2},
- {/*s1*/ RISCV::X9, -3},
- {/*s2*/ RISCV::X18, -4},
- {/*s3*/ RISCV::X19, -5},
- {/*s4*/ RISCV::X20, -6},
- {/*s5*/ RISCV::X21, -7},
- {/*s6*/ RISCV::X22, -8},
- {/*s7*/ RISCV::X23, -9},
- {/*s8*/ RISCV::X24, -10},
- {/*s9*/ RISCV::X25, -11},
- {/*s10*/ RISCV::X26, -12},
- {/*s11*/ RISCV::X27, -13}
-};
-
-bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
- Register Reg,
- int &FrameIdx) const {
- const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
- if (!RVFI->useSaveRestoreLibCalls(MF) && !RVFI->isPushable(MF))
- return false;
-
- const auto *FII =
- llvm::find_if(FixedCSRFIMap, [&](auto P) { return P.first == Reg; });
- if (FII == std::end(FixedCSRFIMap))
- return false;
-
- FrameIdx = FII->second;
- return true;
-}
-
void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator II,
const DebugLoc &DL, Register DestReg,
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index 8b729caa5f713..431ea23b3e2d0 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -35,9 +35,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
const uint32_t *getNoPreservedMask() const override;
- bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
- int &FrameIdx) const override;
-
// Update DestReg to have the value SrcReg plus an offset. This is
// used during frame layout, and we may need to ensure that if we
// split the offset internally that the DestReg is always aligned,
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
index 5c55113fc9749..d08cf577b1bdd 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
@@ -731,11 +731,11 @@ define void @caller_aligned_stack() {
; ILP32E-FPELIM-SAVE-RESTORE-LABEL: caller_aligned_stack:
; ILP32E-FPELIM-SAVE-RESTORE: # %bb.0:
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: call t0, __riscv_save_1
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, sp, -48
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_def_cfa_offset 56
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, sp, -56
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_def_cfa_offset 64
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_offset ra, -4
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_offset s0, -8
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi s0, sp, 56
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi s0, sp, 64
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_def_cfa s0, 0
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: andi sp, sp, -16
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: li a0, 18
@@ -776,18 +776,18 @@ define void @caller_aligned_stack() {
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: li a4, 13
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw a6, 32(sp)
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: call callee_aligned_stack
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, s0, -56
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, sp, 48
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, s0, -64
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, sp, 56
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: tail __riscv_restore_1
;
; ILP32E-WITHFP-SAVE-RESTORE-LABEL: caller_aligned_stack:
; ILP32E-WITHFP-SAVE-RESTORE: # %bb.0:
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: call t0, __riscv_save_1
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi sp, sp, -48
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_def_cfa_offset 56
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi sp, sp, -56
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_def_cfa_offset 64
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_offset ra, -4
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_offset s0, -8
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi s0, sp, 56
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi s0, sp, 64
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_def_cfa s0, 0
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: andi sp, sp, -16
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: li a0, 18
@@ -828,8 +828,8 @@ define void @caller_aligned_stack() {
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: li a4, 13
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw a6, 32(sp)
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: call callee_aligned_stack
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi sp, s0, -56
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi sp, sp, 48
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi sp, s0, -64
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi sp, sp, 56
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: tail __riscv_restore_1
%1 = call i32 @callee_aligned_stack(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
@@ -1431,11 +1431,11 @@ define i32 @caller_large_scalars() {
; ILP32E-FPELIM-SAVE-RESTORE-LABEL: caller_large_scalars:
; ILP32E-FPELIM-SAVE-RESTORE: # %bb.0:
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: call t0, __riscv_save_1
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, sp, -32
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_def_cfa_offset 40
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, sp, -40
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_def_cfa_offset 48
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_offset ra, -4
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_offset s0, -8
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi s0, sp, 40
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi s0, sp, 48
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: .cfi_def_cfa s0, 0
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: andi sp, sp, -16
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: lui a0, 524272
@@ -1443,26 +1443,26 @@ define i32 @caller_large_scalars() {
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw zero, 8(sp)
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw zero, 4(sp)
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw zero, 0(sp)
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw zero, 36(sp)
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw zero, 32(sp)
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw zero, 28(sp)
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw zero, 24(sp)
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw zero, 20(sp)
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: li a2, 1
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi a0, sp, 16
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi a0, sp, 24
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: mv a1, sp
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw a2, 16(sp)
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: sw a2, 24(sp)
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: call callee_large_scalars
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, s0, -40
-; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, sp, 32
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, s0, -48
+; ILP32E-FPELIM-SAVE-RESTORE-NEXT: addi sp, sp, 40
; ILP32E-FPELIM-SAVE-RESTORE-NEXT: tail __riscv_restore_1
;
; ILP32E-WITHFP-SAVE-RESTORE-LABEL: caller_large_scalars:
; ILP32E-WITHFP-SAVE-RESTORE: # %bb.0:
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: call t0, __riscv_save_1
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi sp, sp, -32
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_def_cfa_offset 40
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi sp, sp, -40
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_def_cfa_offset 48
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_offset ra, -4
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_offset s0, -8
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi s0, sp, 40
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi s0, sp, 48
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: .cfi_def_cfa s0, 0
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: andi sp, sp, -16
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: lui a0, 524272
@@ -1470,16 +1470,16 @@ define i32 @caller_large_scalars() {
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw zero, 8(sp)
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw zero, 4(sp)
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw zero, 0(sp)
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw zero, 36(sp)
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw zero, 32(sp)
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw zero, 28(sp)
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw zero, 24(sp)
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw zero, 20(sp)
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: li a2, 1
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi a0, sp, 16
+; ILP32E-WITHFP-SAVE-RESTORE-NEXT: addi a0, sp, 24
; ILP32E-WITHFP-SAVE-RESTORE-NEXT: mv a1, sp
-; ILP32E-WITHFP-SAVE-RESTORE-NEXT: sw a2, 16(sp)
+; ILP32E-WITHFP-SA...
[truncated]
|
francisvm
approved these changes
Feb 12, 2024
| @@ -1403,6 +1361,93 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const { | |||
| return 0; | |||
| } | |||
|
|
|||
| // Frame indexes representing locations of CSRs which are given a fixed location | |||
| // by save/restore libcalls or Zcmp Push/Pop. | |||
| static const std::pair<unsigned, int> FixedCSRFIMap[] = { | |||
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Suggested change
| static const std::pair<unsigned, int> FixedCSRFIMap[] = { | |
| static const std::pair<Register, int> FixedCSRFIMap[] = { |
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It should probably be MCPhysReg
| // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indices to | ||
| // registers which can be saved by Zcmp Push. | ||
| if (CS.getFrameIdx() < 0) | ||
| if (llvm::is_contained(AllPopRegs, CS.getReg().id())) |
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Should we merge AllPopRegs and FixedCSRFIMap?
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…ave-restore/Zcmp.
PEI previously used fake frame indices for these callee saved registers. These fake frame indices are not register with MachineFrameInfo. This required them to be deleted form CalleeSavedInfo after PEI to avoid breaking later passes. See #79535
Unfortunately, removing the registers from CalleeSavedInfo pessimizes Interprocedural Register Allocation. The RegUsageInfoCollector pass runs after PEI and uses CalleeSavedInfo.
This patch replaces #79535 by properly creating fixed stack objects through MachineFrameInfo. This changes the stack size and offsets returned by MachineFrameInfo which requires changes to how RISCVFrameLowering uses that information.
In addition to the individual object for each register, I've also create a single large fixed object that covers the entire stack area covered by cm.push or the libcalls. cm.push must always push a multiple of 16 bytes and the save restore libcall pushes a multiple of stack align. I think this leaves holes in the stack where we could spill other registers, but it matches what we did previously. Maybe we can optimize this in the future.
The only test changes are due to stack alignment handling after the callee save registers. Since we now have the fixed objects, on the stack the offset is non-zero when an aligned object is processed so the offset gets rounded up, increasing the stack size.
I suspect we might need some more updates for RVV related code. There is very little or maybe even no testing of RVV mixed with Zcmp and save-restore.