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[AMDGPU] Set predicates more consistently for BUF instructions #81865

Merged
merged 5 commits into from
Feb 17, 2024
Merged

[AMDGPU] Set predicates more consistently for BUF instructions #81865

merged 5 commits into from
Feb 17, 2024

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jayfoad
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@jayfoad jayfoad commented Feb 15, 2024

Set DecoderNamespace and AssemblerPredicate in the base class for Real
instructions for each subtarget. This avoids some ad hoc "let" around
groups of instructions definitions, and fixes some missed cases like
BUFFER_GL0_INV_gfx10 which was missing DecoderNamespace.

@jayfoad
[AMDGPU] Set predicates more consistently for GFX10+ BUF instructions
2fe77dc 
Set DecoderNamespace and AssemblerPredicate in the base class for Real
instructions for each subtarget. This avoids some ad hoc "let" around
groups of instructions definitions, and fixes some missed cases like
BUFFER_GL0_INV_gfx10 which was missing DecoderNamespace.
@llvmbot
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llvmbot commented Feb 15, 2024

@llvm/pr-subscribers-backend-amdgpu

Author: Jay Foad (jayfoad)

Changes

Set DecoderNamespace and AssemblerPredicate in the base class for Real
instructions for each subtarget. This avoids some ad hoc "let" around
groups of instructions definitions, and fixes some missed cases like
BUFFER_GL0_INV_gfx10 which was missing DecoderNamespace.

Full diff: https://github.com/llvm/llvm-project/pull/81865.diff

1 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/BUFInstructions.td (+127-136)
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 43df6c36f47eb6..26d34db4d73fc8 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -2308,7 +2308,8 @@ class MUBUF_Real_gfx11<bits<8> op, MUBUF_Pseudo ps,
   let Inst{53}    = ps.tfe;
   let Inst{54}    = ps.offen;
   let Inst{55}    = ps.idxen;
-  let SubtargetPredicate = isGFX11Only;
+  let AssemblerPredicate = isGFX11Only;
+  let DecoderNamespace = "GFX11";
 }
 
 class Base_MUBUF_Real_Atomic_gfx11<bits<8> op, MUBUF_Pseudo ps,
@@ -2332,7 +2333,8 @@ class MUBUF_Real_gfx10<bits<8> op, MUBUF_Pseudo ps> :
     Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.GFX10> {
   let Inst{15} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlc_value);
   let Inst{25} = op{7};
-  let SubtargetPredicate = isGFX10Only;
+  let AssemblerPredicate = isGFX10Only;
+  let DecoderNamespace = "GFX10";
 }
 
 class MUBUF_Real_gfx6_gfx7<bits<8> op, MUBUF_Pseudo ps> :
@@ -2406,7 +2408,8 @@ class VBUFFER_MUBUF_Real_gfx12<bits<8> op, MUBUF_Pseudo ps,
   // print BUF_FMT_INVALID for format 0.
   let Inst{55} = 0b1;
   let Inst{21-14} = op;
-  let SubtargetPredicate = isGFX12Only;
+  let AssemblerPredicate = isGFX12Only;
+  let DecoderNamespace = "GFX12";
 }
 
 class VBUFFER_MTBUF_Real_gfx12<bits<4> op, MTBUF_Pseudo ps,
@@ -2420,6 +2423,8 @@ class VBUFFER_MTBUF_Real_gfx12<bits<4> op, MTBUF_Pseudo ps,
   let Inst{17-14} = op;
   let Inst{21-18} = 0b1000;
   let Inst{61-55} = format;
+  let AssemblerPredicate = isGFX12Plus;
+  let DecoderNamespace = "GFX12";
 }
 
 //===----------------------------------------------------------------------===//
@@ -2449,21 +2454,17 @@ class VBUFFER_MUBUF_Real_gfx12_impl<bits<8> op, string ps_name, string real_name
   VBUFFER_MUBUF_Real_gfx12<op, !cast<MUBUF_Pseudo>(ps_name), real_name>;
 
 multiclass MUBUF_Real_AllAddr_gfx11_Renamed_Impl2<bits<8> op, string real_name> {
-  let DecoderNamespace = "GFX11" in {
-    def _BOTHEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_BOTHEN", real_name>;
-    def _IDXEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_IDXEN", real_name>;
-    def _OFFEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_OFFEN", real_name>;
-    def _OFFSET_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_OFFSET", real_name>;
-  }
+  def _BOTHEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_BOTHEN", real_name>;
+  def _IDXEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_IDXEN", real_name>;
+  def _OFFEN_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_OFFEN", real_name>;
+  def _OFFSET_gfx11 : MUBUF_Real_gfx11_impl<op, NAME # "_OFFSET", real_name>;
 }
 
 multiclass MUBUF_Real_AllAddr_gfx12_Renamed_Impl2<bits<8> op, string real_name> {
-  let DecoderNamespace = "GFX12" in {
-    def _BOTHEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_BOTHEN", real_name>;
-    def _IDXEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_IDXEN", real_name>;
-    def _OFFEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_OFFEN", real_name>;
-    def _OFFSET_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_OFFSET", real_name>;
-  }
+  def _BOTHEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_BOTHEN", real_name>;
+  def _IDXEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_IDXEN", real_name>;
+  def _OFFEN_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_OFFEN", real_name>;
+  def _OFFSET_gfx12 : VBUFFER_MUBUF_Real_gfx12_impl<op, NAME # "_VBUFFER_OFFSET", real_name>;
 }
 
 multiclass MUBUF_Real_AllAddr_gfx11_gfx12_Renamed_Impl2<bits<8> op, string real_name> :
@@ -2506,40 +2507,36 @@ class MUBUF_Real_Atomic_gfx12_impl<bits<8> op, string ps_name,
 
 multiclass MUBUF_Real_Atomic_gfx11_Renamed_impl<bits<8> op, bit is_return,
                                                 string real_name> {
-  let DecoderNamespace = "GFX11" in {
-    defvar Rtn = !if(!eq(is_return, 1), "_RTN", "");
-    def _BOTHEN#Rtn#_gfx11 :
-      MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_BOTHEN" # Rtn, real_name>,
-      AtomicNoRet<NAME # "_BOTHEN_gfx11", is_return>;
-    def _IDXEN#Rtn#_gfx11 :
-      MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_IDXEN" # Rtn, real_name>,
-      AtomicNoRet<NAME # "_IDXEN_gfx11", is_return>;
-    def _OFFEN#Rtn#_gfx11 :
-      MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFEN" # Rtn, real_name>,
-      AtomicNoRet<NAME # "_OFFEN_gfx11", is_return>;
-    def _OFFSET#Rtn#_gfx11 :
-      MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFSET" # Rtn, real_name>,
-      AtomicNoRet<NAME # "_OFFSET_gfx11", is_return>;
-  }
+  defvar Rtn = !if(!eq(is_return, 1), "_RTN", "");
+  def _BOTHEN#Rtn#_gfx11 :
+    MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_BOTHEN" # Rtn, real_name>,
+    AtomicNoRet<NAME # "_BOTHEN_gfx11", is_return>;
+  def _IDXEN#Rtn#_gfx11 :
+    MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_IDXEN" # Rtn, real_name>,
+    AtomicNoRet<NAME # "_IDXEN_gfx11", is_return>;
+  def _OFFEN#Rtn#_gfx11 :
+    MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFEN" # Rtn, real_name>,
+    AtomicNoRet<NAME # "_OFFEN_gfx11", is_return>;
+  def _OFFSET#Rtn#_gfx11 :
+    MUBUF_Real_Atomic_gfx11_impl<op, NAME # "_OFFSET" # Rtn, real_name>,
+    AtomicNoRet<NAME # "_OFFSET_gfx11", is_return>;
 }
 
 multiclass MUBUF_Real_Atomic_gfx12_Renamed_impl<bits<8> op, bit is_return,
                                                 string real_name> {
-  let DecoderNamespace = "GFX12" in {
-    defvar Rtn = !if(!eq(is_return, 1), "_RTN", "");
-    def _BOTHEN#Rtn#_gfx12 :
-      MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_BOTHEN" # Rtn, real_name>,
-      AtomicNoRet<NAME # "_BOTHEN_gfx12", is_return>;
-    def _IDXEN#Rtn#_gfx12 :
-      MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_IDXEN" # Rtn, real_name>,
-      AtomicNoRet<NAME # "_IDXEN_gfx12", is_return>;
-    def _OFFEN#Rtn#_gfx12 :
-      MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFEN" # Rtn, real_name>,
-      AtomicNoRet<NAME # "_OFFEN_gfx12", is_return>;
-    def _OFFSET#Rtn#_gfx12 :
-      MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFSET" # Rtn, real_name>,
-      AtomicNoRet<NAME # "_OFFSET_gfx12", is_return>;
-  }
+  defvar Rtn = !if(!eq(is_return, 1), "_RTN", "");
+  def _BOTHEN#Rtn#_gfx12 :
+    MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_BOTHEN" # Rtn, real_name>,
+    AtomicNoRet<NAME # "_BOTHEN_gfx12", is_return>;
+  def _IDXEN#Rtn#_gfx12 :
+    MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_IDXEN" # Rtn, real_name>,
+    AtomicNoRet<NAME # "_IDXEN_gfx12", is_return>;
+  def _OFFEN#Rtn#_gfx12 :
+    MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFEN" # Rtn, real_name>,
+    AtomicNoRet<NAME # "_OFFEN_gfx12", is_return>;
+  def _OFFSET#Rtn#_gfx12 :
+    MUBUF_Real_Atomic_gfx12_impl<op, NAME # "_VBUFFER_OFFSET" # Rtn, real_name>,
+    AtomicNoRet<NAME # "_OFFSET_gfx12", is_return>;
 }
 
 multiclass MUBUF_Real_Atomic_gfx11_gfx12_Renamed_impl<bits<8> op, bit is_return,
@@ -2578,10 +2575,8 @@ multiclass MUBUF_Real_Atomic_gfx11_gfx12_Renamed_gfx12_Renamed<bits<8> op, strin
   def : Mnem_gfx12<gfx11_name, gfx12_name>;
 }
 
-let DecoderNamespace = "GFX11" in {
 def BUFFER_GL0_INV_gfx11          : MUBUF_Real_gfx11<0x02B, BUFFER_GL0_INV>;
 def BUFFER_GL1_INV_gfx11          : MUBUF_Real_gfx11<0x02C, BUFFER_GL1_INV>;
-}
 
 defm BUFFER_LOAD_DWORD            : MUBUF_Real_AllAddr_gfx11_gfx12_Renamed<0x014, "buffer_load_b32">;
 defm BUFFER_LOAD_DWORDX2          : MUBUF_Real_AllAddr_gfx11_gfx12_Renamed<0x015, "buffer_load_b64">;
@@ -2669,64 +2664,62 @@ defm BUFFER_ATOMIC_PK_ADD_BF16    : MUBUF_Real_Atomic_gfx12<0x05a>;
 // MUBUF - GFX10.
 //===----------------------------------------------------------------------===//
 
-let DecoderNamespace = "GFX10" in {
-  multiclass MUBUF_Real_AllAddr_Helper_gfx10<bits<8> op> {
-    def _BOTHEN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
-    def _IDXEN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
-    def _OFFEN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
-    def _OFFSET_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
-  }
-  multiclass MUBUF_Real_AllAddr_gfx10<bits<8> op> {
-    defm NAME : MUBUF_Real_AllAddr_Helper_gfx10<op>;
-    defm _TFE : MUBUF_Real_AllAddr_Helper_gfx10<op>;
-  }
-  multiclass MUBUF_Real_AllAddr_Lds_gfx10<bits<8> op, bit isTFE = 0> {
-    def _OFFSET_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
-    def _OFFEN_gfx10  : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
-    def _IDXEN_gfx10  : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
-    def _BOTHEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
+multiclass MUBUF_Real_AllAddr_Helper_gfx10<bits<8> op> {
+  def _BOTHEN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
+  def _IDXEN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
+  def _OFFEN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
+  def _OFFSET_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
+}
+multiclass MUBUF_Real_AllAddr_gfx10<bits<8> op> {
+  defm NAME : MUBUF_Real_AllAddr_Helper_gfx10<op>;
+  defm _TFE : MUBUF_Real_AllAddr_Helper_gfx10<op>;
+}
+multiclass MUBUF_Real_AllAddr_Lds_gfx10<bits<8> op, bit isTFE = 0> {
+  def _OFFSET_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
+  def _OFFEN_gfx10  : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
+  def _IDXEN_gfx10  : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
+  def _BOTHEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
 
-    if !not(isTFE) then {
-      def _LDS_OFFSET_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>;
-      def _LDS_OFFEN_gfx10  : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>;
-      def _LDS_IDXEN_gfx10  : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>;
-      def _LDS_BOTHEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>;
-    }
-  }
-  multiclass MUBUF_Real_Atomics_RTN_gfx10<bits<8> op> {
-    def _BOTHEN_RTN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>,
-      AtomicNoRet<NAME # "_BOTHEN_gfx10", 1>;
-    def _IDXEN_RTN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>,
-      AtomicNoRet<NAME # "_IDXEN_gfx10", 1>;
-    def _OFFEN_RTN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>,
-      AtomicNoRet<NAME # "_OFFEN_gfx10", 1>;
-    def _OFFSET_RTN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>,
-      AtomicNoRet<NAME # "_OFFSET_gfx10", 1>;
-  }
-  multiclass MUBUF_Real_Atomics_gfx10<bits<8> op> :
-      MUBUF_Real_Atomics_RTN_gfx10<op> {
-    def _BOTHEN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
-      AtomicNoRet<NAME # "_BOTHEN_gfx10", 0>;
-    def _IDXEN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
-      AtomicNoRet<NAME # "_IDXEN_gfx10", 0>;
-    def _OFFEN_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
-      AtomicNoRet<NAME # "_OFFEN_gfx10", 0>;
-    def _OFFSET_gfx10 :
-      MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
-      AtomicNoRet<NAME # "_OFFSET_gfx10", 0>;
+  if !not(isTFE) then {
+    def _LDS_OFFSET_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>;
+    def _LDS_OFFEN_gfx10  : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>;
+    def _LDS_IDXEN_gfx10  : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>;
+    def _LDS_BOTHEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>;
   }
-} // End DecoderNamespace = "GFX10"
+}
+multiclass MUBUF_Real_Atomics_RTN_gfx10<bits<8> op> {
+  def _BOTHEN_RTN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>,
+    AtomicNoRet<NAME # "_BOTHEN_gfx10", 1>;
+  def _IDXEN_RTN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>,
+    AtomicNoRet<NAME # "_IDXEN_gfx10", 1>;
+  def _OFFEN_RTN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>,
+    AtomicNoRet<NAME # "_OFFEN_gfx10", 1>;
+  def _OFFSET_RTN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>,
+    AtomicNoRet<NAME # "_OFFSET_gfx10", 1>;
+}
+multiclass MUBUF_Real_Atomics_gfx10<bits<8> op> :
+    MUBUF_Real_Atomics_RTN_gfx10<op> {
+  def _BOTHEN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
+    AtomicNoRet<NAME # "_BOTHEN_gfx10", 0>;
+  def _IDXEN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
+    AtomicNoRet<NAME # "_IDXEN_gfx10", 0>;
+  def _OFFEN_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
+    AtomicNoRet<NAME # "_OFFEN_gfx10", 0>;
+  def _OFFSET_gfx10 :
+    MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
+    AtomicNoRet<NAME # "_OFFSET_gfx10", 0>;
+}
 
 defm BUFFER_STORE_BYTE_D16_HI     : MUBUF_Real_AllAddr_gfx10<0x019>;
 defm BUFFER_STORE_SHORT_D16_HI    : MUBUF_Real_AllAddr_gfx10<0x01b>;
@@ -2944,6 +2937,8 @@ class Base_MTBUF_Real_gfx11<bits<4> op, MTBUF_Pseudo ps,
   let Inst{53}    = ps.tfe;
   let Inst{54}    = ps.offen;
   let Inst{55}    = ps.idxen;
+  let AssemblerPredicate = isGFX11Only;
+  let DecoderNamespace = "GFX11";
 }
 
 class Base_MTBUF_Real_gfx6_gfx7_gfx10<bits<3> op, MTBUF_Pseudo ps, int ef> :
@@ -2960,27 +2955,23 @@ class Base_MTBUF_Real_gfx6_gfx7_gfx10<bits<3> op, MTBUF_Pseudo ps, int ef> :
 //===----------------------------------------------------------------------===//
 
 multiclass MTBUF_Real_AllAddr_gfx11_gfx12_Renamed_Impl<bits<4> op, string real_name> {
-  let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
-    def _BOTHEN_gfx11 :
-      Base_MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN"), real_name>;
-    def _IDXEN_gfx11 :
-      Base_MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN"), real_name>;
-    def _OFFEN_gfx11 :
-      Base_MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN"), real_name>;
-    def _OFFSET_gfx11 :
-      Base_MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET"), real_name>;
-  }
-
-  let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in {
-    def _BOTHEN_gfx12 :
-      VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_BOTHEN"), real_name>;
-    def _IDXEN_gfx12 :
-      VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_IDXEN"), real_name>;
-    def _OFFEN_gfx12 :
-      VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_OFFEN"), real_name>;
-    def _OFFSET_gfx12 :
-      VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_OFFSET"), real_name>;
-  }
+  def _BOTHEN_gfx11 :
+    Base_MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN"), real_name>;
+  def _IDXEN_gfx11 :
+    Base_MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN"), real_name>;
+  def _OFFEN_gfx11 :
+    Base_MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN"), real_name>;
+  def _OFFSET_gfx11 :
+    Base_MTBUF_Real_gfx11<op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET"), real_name>;
+
+  def _BOTHEN_gfx12 :
+    VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_BOTHEN"), real_name>;
+  def _IDXEN_gfx12 :
+    VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_IDXEN"), real_name>;
+  def _OFFEN_gfx12 :
+    VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_OFFEN"), real_name>;
+  def _OFFSET_gfx12 :
+    VBUFFER_MTBUF_Real_gfx12<op, !cast<MTBUF_Pseudo>(NAME#"_VBUFFER_OFFSET"), real_name>;
 }
 
 multiclass MTBUF_Real_AllAddr_gfx11_gfx12_Impl<bits<4> op, MTBUF_Pseudo ps>
@@ -3022,20 +3013,20 @@ class MTBUF_Real_gfx10<bits<4> op, MTBUF_Pseudo ps> :
   let Inst{15} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlc_value);
   let Inst{25-19} = format;
   let Inst{53} = op{3};
+  let AssemblerPredicate = isGFX10Only;
+  let DecoderNamespace = "GFX10";
 }
 
-let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
-  multiclass MTBUF_Real_AllAddr_gfx10<bits<4> op> {
-    def _BOTHEN_gfx10 :
-      MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>;
-    def _IDXEN_gfx10 :
-      MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>;
-    def _OFFEN_gfx10 :
-      MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
-    def _OFFSET_gfx10 :
-      MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>;
-  }
-} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
+multiclass MTBUF_Real_AllAddr_gfx10<bits<4> op> {
+  def _BOTHEN_gfx10 :
+    MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>;
+  def _IDXEN_gfx10 :
+    MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>;
+  def _OFFEN_gfx10 :
+    MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
+  def _OFFSET_gfx10 :
+    MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>;
+}
 
 defm TBUFFER_LOAD_FORMAT_D16_X     : MTBUF_Real_AllAddr_gfx10<0x008>;
 defm TBUFFER_LOAD_FORMAT_D16_XY    : MTBUF_Real_AllAddr_gfx10<0x009>;

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jayfoad commented Feb 15, 2024

I didn't bother to do this for older (pre-GXF10) targets.

@jayfoad
Standardize on isGFX12Only instead of isGFX12Plus
9846fe3 
This will have to be revised anyway when the next architecture comes
along.
@jayfoad
Same for GFX6 and GFX7
704f2fa 
This fixes another case which was missing a suitable DecoderNamespace
definition: BUFFER_WBINVL1_gfx6_gfx7
@jayfoad
Merge remote-tracking branch 'origin/main' into gfx10-buf-predicates
1aea0ec
@jayfoad
Stop using DecoderTableAMDGPU64
9d70bef 
There are no 64-bit instructions left in the AMDGPU namespace so
tablegen no longer generates this table.
@jayfoad jayfoad changed the title [AMDGPU] Set predicates more consistently for GFX10+ BUF instructions [AMDGPU] Set predicates more consistently for BUF instructions Feb 16, 2024
@jayfoad jayfoad merged commit ded3ca2 into llvm:main Feb 17, 2024
4 checks passed
@jayfoad jayfoad deleted the gfx10-buf-predicates branch February 17, 2024 13:19
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@rampitec rampitec rampitec approved these changes

@piotrAMD piotrAMD Awaiting requested review from piotrAMD

@mbrkusanin mbrkusanin Awaiting requested review from mbrkusanin

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@jayfoad @llvmbot @rampitec